Encoding and decoding architecture for high-speed data communication system and related physical layer circuit, transmitter and receiver and communication system thereof

Abstract

The present invention discloses a physical layer circuit for a transmitter and a method thereof, a physical layer circuit for a receiver and a method thereof, and a communication system based on a multi-wire communication connection for a high-speed serial data communication system, such as, coding and decoding architecture of the physical layer in the MIPI C-PHY. Embodiments of the present invention include encoding chains and decoding chains adaptable to physical layer circuits of transmitters and receivers, respectively. The physical layer circuit of a transmitter includes: an encoding chain and a parallel-to-serial (P2S) converter. The encoding chain having a plurality of encoding unit coupled in series, and is arranged to receive a plurality of first symbols and convert each of the symbols to a corresponding wire state, thereby to generate a plurality of wire states. The P2S converter is coupled to the encoding chain, arranged to receive the plurality of wire states and serializethe plurality of wire states to provide a sequence of wire states.

Description

Technical field [0001] The present invention relates to high-speed data communication, in particular to the encoding and decoding architecture of a high-speed serial data communication system and related methods, physical layer circuits, transmitters and receivers, and communication systems. Background technique [0002] Mobile devices such as smart phones contain various components for different purposes, such as application processors, displays, and CMOS image sensors. These elements need to be interconnected through a physical interface. For example, the application processor can provide frame data to the display through an interface to present visual content. Alternatively, the CMOS image sensor can provide the sensed image data to the application processor through an interface to output photos or videos. [0003] The MIPI specification formulated by the Mobile Industry Processor Interface (MIPI) alliance is widely used in the signal communication and data transmission between...

AI Technical Summary

Problems solved by technology

In this way, the low supply voltage and the huge internal logic gate count (gate count) in the hardware components will make the hardware components (such as combinational logic) in complex serial communication systems (such as MIPI C-PHY communication systems) circuit) delay (eg, logic gate delay) is difficult to shorten

Therefore, timing conflicts may occur if the overall logic gate delay of the hardware element cannot keep up with the timing requirements of the unit interval of the transfer

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