Double-layer base region SiC NPN integrated transistor and preparation method thereof
A production method and transistor technology, applied in the direction of transistor, semiconductor/solid-state device manufacturing, semiconductor devices, etc., can solve the problem of large gain β temperature drift, etc., to achieve the effect of increasing gain and reducing the degree of drift
Active Publication Date: 2019-06-14
XIAN UNIV OF TECH
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Problems solved by technology
[0004] The purpose of the present invention is to provide a double-layer base SiC NPN integrated transistor to solve the problem that the gain β of the existing SiCNPN integrated transistor drifts too much with temperature
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[0060] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.
[0061] The upper and lower positions in the following text are indicated by figure 1 Shown is the reference, the actual position and so on.
[0062] like figure 1 As shown, the structure of the double-layer base SiC integrated transistor of the present invention includes a substrate 1, and the material of the substrate 1 is high-purity semi-insulating SiC; the thickness of the substrate 1 is 10 μm-1000 μm, and the upper and lower end surface areas of the substrate 1 are both 0.01nm 2 -100cm 2 ;
[0063] The upper surface of the substrate 1 is provided with a first epitaxial layer 2, that is, the collector region of the NPN transistor, the material of the first epitaxial layer 2 is n-type SiC, and the doping concentration of the first epitaxial layer 2 is 1e17cm -3 -1e22cm -3 , the thickness of the first epitaxial layer 2 is 0.01 μm-5 μm, ...
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Abstract
The invention discloses a double-layer base region SiC NPN integrated transistor which comprises a substrate and a passivation layer, wherein a first epitaxial layer, a second epitaxial layer, a thirdepitaxial layer, a fourth epitaxial layer and a fifth epitaxial layer are sequentially arranged on the upper end surface of the substrate; the fifth epitaxial layer and the fourth epitaxial layer form a third boss; the third epitaxial layer and the second epitaxial layer form a second boss; the first epitaxial layer is a first boss; the passivation layer covers the external surfaces of the thirdboss, the second boss and the first boss and the upper end surface of the substrate; a first electrode is arranged on the upper end surface of the third boss; a second electrode is arranged on the upper end surface of the second boss; and a third electrode is arranged on the upper end surface of the first boss. The invention further discloses a preparation method of the double-layer base region SiC NPN integrated transistor. A base region of the double-layer base region SiC NPN integrated transistor adopts a low-high-junction double-layer structure, so that the drift degree of a gain beta along with the temperature is reduced.
Description
technical field [0001] The invention belongs to the field of semiconductor integrated circuits, relates to a double-layer base region SiC NPN integrated transistor, and also relates to a manufacturing method of the above-mentioned double-layer base region SiC NPN integrated transistor. Background technique [0002] Silicon carbide (SiC) material has the advantages of high forbidden band width, high critical breakdown electric field, high thermal conductivity and high saturation electron drift speed. Approved. Among them, SiC bipolar integrated circuits are more suitable for high temperature environments because there is no gate oxide reliability problem. Due to the unique properties of SiC materials, its SiC NPN integrated transistors and their manufacturing processes are not compatible with the existing technology. The common emitter current gain β of SiC NPN integrated transistors drifts seriously with temperature, and the impact on the performance of integrated circuits ...
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Login to View More IPC IPC(8): H01L29/10H01L29/16H01L21/331H01L29/73
Inventor 蒲红斌唐新宇王曦安丽琪刘青李佳琪杜利祥
Owner XIAN UNIV OF TECH