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Virtual test method, apparatus and device and storage medium

A technology of virtual testing and equipment, applied in the computer field, can solve the problems of high design difficulty, increase of chip area and packaging cost, etc., achieve the effect of reducing hardware development cost, improving chip testing efficiency, and saving hardware resources

Active Publication Date: 2019-06-21
上海燧原智能科技有限公司 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In the prior art, the usual method is to increase the pins used by dedicated ATPG, but it will increase the chip area and packaging cost, and with the development of 2.5D and 3D packaging, the design of such dedicated test pins becomes more and more difficult. higher

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  • Virtual test method, apparatus and device and storage medium
  • Virtual test method, apparatus and device and storage medium
  • Virtual test method, apparatus and device and storage medium

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Embodiment Construction

[0026] The embodiments of the present invention will be further described in detail below in conjunction with the drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the embodiments of the present invention, rather than to limit the embodiments of the present invention. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all structures related to the embodiments of the present invention.

[0027] figure 1 It is a flow chart of a virtual testing method provided by the embodiment of the present invention. This embodiment is applicable to virtual testing. The method can be executed by a device such as a computer, and specifically includes the following steps:

[0028] Step S101 , setting the current test mode as a virtual test mode, in which the control signals associated with the test are taken over by the virtual test register.

[0029] The chip needs ...

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Abstract

The embodiment of the invention discloses a virtual test method, apparatus and device and a storage medium. The method comprises the steps of: setting a current test mode as a virtual test mode, in the virtual test mode, taking over and testing associated control signals by a virtual test register; generating transmission clock by the virtual test register for test of link load; and after the testof the link load is completed, generating capture clock by the virtual test register, and performing capture of the test result. The scheme improves the chip test efficiency and saves the hardware resources.

Description

technical field [0001] The embodiment of the present invention relates to computer technology, in particular to a virtual testing method, device, equipment and storage medium. Background technique [0002] The current SOC (System on Chip, system on a chip) chip usually consists of dozens of embedded identical cores, and depending on the application, the SOC can also include multiple replicated high-speed physical bodies for die and external storage, memory between communication. [0003] As the scale of the chip gradually expands, the total number of scan channels used for testing greatly exceeds the number of functional GPIOs that can be reused as scan channels. In the prior art, the usual method is to increase the pins used by dedicated ATPG, but it will increase the chip area and packaging cost, and with the development of 2.5D and 3D packaging, the design of such dedicated test pins becomes more and more difficult. higher. Contents of the invention [0004] The embo...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
Inventor 马海英郭锐韩晶
Owner 上海燧原智能科技有限公司