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Display

A display, thin film transistor technology, applied in the field of displays with a new test pad layout design, can solve problems such as limited space

Inactive Publication Date: 2019-07-26
SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of this, the present invention provides a new display, which adopts a special design that can increase the arrangement space of the test pads, digs out an additional area of ​​the color filter glass, that is, the enlarged area on the side of the chip, and places the chip test pads separately In this area, to solve the problem of limited space in the corner of the chip, and to avoid the surface as much as possible to use three cuts, to achieve the effect of saving production capacity and reduce the process steps and time

Method used

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Embodiment 1

[0030] Accordingly, according to an embodiment 1 of the present invention, the present invention provides a display 300, see image 3 . image 3 It is a schematic diagram of arrangement of chip test pads of a display according to an embodiment of the present invention. like image 3 As shown, specifically, a display 300 according to an embodiment of the present invention includes: a thin film transistor (TFT) substrate 310; a color filter (CF) substrate 320, configured on the TFT substrate 310 and exposing the TFT substrate The first edge portion of the upper surface of the TFT substrate 310, wherein at least two corners of the CF substrate 320 each have a gap, the gap exposes the upper surface of the TFT substrate 310, forming at least two gap regions 312, 313 on the upper surface of the TFT substrate 310 ; and a plurality of chip test pads 330 are disposed on the first edge portion 310 a and the notch regions 312 , 313 .

[0031] continue to see image 3 , in Embodiment ...

Embodiment 2

[0039] According to an embodiment 2 of the present invention, the present invention provides a display 400, see Figure 4 . Figure 4 It is a schematic diagram of arrangement of chip test pads of a display according to another embodiment of the present invention. like Figure 4 As shown, specifically, a display 400 according to an embodiment of the present invention includes: a thin film transistor (TFT) substrate 410; a color filter (CF) substrate 420, configured on the TFT substrate 410 and exposing the TFT substrate The first edge portion of the upper surface of the TFT substrate 410, wherein at least two corners of the CF substrate 420 each have a gap, the gap exposes the upper surface of the TFT substrate 410, forming at least two gap regions 412, 413 On the upper surface of the TFT substrate 410 ; and a plurality of chip test pads 430 are disposed on the first edge portion 410 a and the notch areas 412 , 413 .

[0040] continue to see Figure 4 , in Embodiment 2 of t...

Embodiment 3

[0042] According to an embodiment 3 of the present invention, the present invention provides a display 500, see Figure 5 . Figure 5 It is a schematic diagram of arrangement of chip test pads of a display according to another embodiment of the present invention. like Figure 5 As shown, specifically, a display 500 according to an embodiment of the present invention includes: a thin film transistor (TFT) substrate 510; a color filter (CF) substrate 520, which is disposed on the TFT substrate 510 and exposes the TFT substrate The first edge portion of the upper surface of the TFT substrate 510, wherein at least two corners of the CF substrate 520 each have a gap, the gap exposes the upper surface of the TFT substrate 510, forming at least two gap regions 512, 513 on the upper surface of the TFT substrate 510; and a plurality of chip test pads 530 are disposed on the first edge portion 510a and the notch areas 512, 513.

[0043] continue to see Figure 5 , in Embodiment 3 of...

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Abstract

The invention provides a display comprising a thin film transistor (TFT) substrate; a color film (CF) substrate, wherein the CF substrate is arranged on the TFT substrate and exposes a first edge partof the upper surface of the TFT substrate, at least two corners of the CF substrate are respectively provided with a notch, the notches expose the upper surface of the TFT substrate, and at least twonotch areas are formed on the upper surface of the TFT substrate; and a plurality of chip test pads disposed on the first edge portion and the notch region.

Description

technical field [0001] The invention relates to a display, in particular to a display with a novel arrangement design of test pads. Background technique [0002] Conventional cell test pads are placed on the chip side, and the chip test pads are divided into source (source) signals, array upper gate (GOA) signals, and functional signals (Acom, Cfcom, etc.), For a chip with a gate on array (GOA), the gate signal is mainly a timing signal (CK). As the resolution increases and the pixel size becomes smaller, the distance from the color filter (COF) to the edge of the thin-film transistor (TFT) decreases. To increase the resolution, the number of timing signals needs to be increased, which results in a chip corner space restricted. [0003] figure 1 It is a schematic diagram of the arrangement of chip test pads of a conventional display; figure 2 It is a schematic diagram of the arrangement of chip test pads of another conventional display. like figure 1 and figure 2 As...

Claims

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Application Information

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IPC IPC(8): G09G3/00
CPCG09G3/006
Inventor 李利霞王勐
Owner SHENZHEN CHINA STAR OPTOELECTRONICS SEMICON DISPLAY TECH CO LTD
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