Display

Abstract

The invention provides a display comprising a thin film transistor (TFT) substrate; a color film (CF) substrate, wherein the CF substrate is arranged on the TFT substrate and exposes a first edge partof the upper surface of the TFT substrate, at least two corners of the CF substrate are respectively provided with a notch, the notches expose the upper surface of the TFT substrate, and at least twonotch areas are formed on the upper surface of the TFT substrate; and a plurality of chip test pads disposed on the first edge portion and the notch region.

Description

technical field [0001] The invention relates to a display, in particular to a display with a novel arrangement design of test pads. Background technique [0002] Conventional cell test pads are placed on the chip side, and the chip test pads are divided into source (source) signals, array upper gate (GOA) signals, and functional signals (Acom, Cfcom, etc.), For a chip with a gate on array (GOA), the gate signal is mainly a timing signal (CK). As the resolution increases and the pixel size becomes smaller, the distance from the color filter (COF) to the edge of the thin-film transistor (TFT) decreases. To increase the resolution, the number of timing signals needs to be increased, which results in a chip corner space restricted. [0003] figure 1 It is a schematic diagram of the arrangement of chip test pads of a conventional display; figure 2 It is a schematic diagram of the arrangement of chip test pads of another conventional display. like figure 1 and figure 2 As...

AI Technical Summary

Problems solved by technology

[0006] In view of this, the present invention provides a new display, which adopts a special design that can increase the arrangement space of the test pads, digs out an additional area of ​​the color filter glass, that is, the enlarged area on the side of the chip, and

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