Position marking method and analysis method for failure structure in flip chip
A marking method and flip-chip technology, applied in the direction of semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve the problems of difficult operation of the transverse section of the failed structure, inability to mark the failed structure, low efficiency, etc. Difficulty of operation, accurate marking, and the effect of improving work efficiency
Active Publication Date: 2019-07-30
SUZHOU TF AMD SEMICON CO LTD
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Problems solved by technology
[0004] In the analysis method of the above-mentioned failure structure, because the failure structure existing in the underfill layer cannot be precisely marked, the operation of obtaining the transverse section of the failure structure is difficult and inefficient
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[0030] The application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain related inventions, rather than to limit the invention. It should also be noted that, for ease of description, only parts related to the invention are shown in the drawings.
[0031] It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and embodiments.
[0032] Please refer to the attached Figure 1-3 , the embodiment of the present application provides a method for marking the position of a failure structure in a flip chip. The flip chip includes a stacked chip 1 and a substrate 2, and a plurality of interconnection structures arranged in an arra...
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The invention discloses a position marking method and an analysis method for a failure structure in a flip chip; the position marking method comprises the following steps that the position informationof the failure structure in a bottom filling layer in an array of an interconnection structure is obtained, wherein the position information is expressed in a row and column number of the array; at least a part of a substrate is removed to form an exposed marking surface, wherein one end, deviated away from the chip, of each interconnection structure is located on the marking surface; and the position indicated by the position information is marked on the marking surface. According to the position marking method and the analysis method for the failure structure in the flip chip provided by the invention, by removing at least a part of the substrate to form the marking surface which exposes one end, deviated away from the chip, of each interconnection structure in the array to the externalmarking surface; and then marking is performed on the marking surface according to the position information of the failure structure, so that the purpose of accurately marking the failure structure on the flip chip is achieved, and further the operation difficulty of acquiring the transverse cross section of the failure structure is lowered.
Description
technical field [0001] The present invention generally relates to the field of semiconductor technology, specifically to the field of flip chip technology, and in particular to a position marking method and an analysis method for a failure structure in a flip chip. Background technique [0002] In a flip chip, the functional surface of the semiconductor chip is arranged facing the substrate, and the functional surface of the chip and the substrate are electrically connected through a plurality of conductive interconnection structures. Wherein, a bottom filling layer is filled between the chip and the substrate, and a plurality of interconnection structures are located in the bottom filling layer. [0003] When forming the underfill layer, failure structures may occur due to technical or operational reasons, thereby affecting the performance of the flip chip. When analyzing the above-mentioned failure structure, the position of the failure structure in the underfill layer is...
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Login to View More IPC IPC(8): H01L21/66
CPCH01L22/12
Inventor 王艳何志丹宁福英
Owner SUZHOU TF AMD SEMICON CO LTD