A feedback device and method for improving ddr bus utilization

Abstract

The invention discloses a feedback device and method for improving DDR bus utilization, comprising a command buffer queue module, a monitoring module and a calculation feedback module; the command buffer queue module outputs commands to the calculation feedback module; the monitoring module Identify and monitor the commands entering the command buffer queue, record the order and information of the commands, and communicate with the computing feedback module, and feed back the information of the commands entering the command buffer queue module and leaving the command buffer queue module to the computing device in real time Feedback module; the calculation feedback module performs bank-by-bank statistics on the command information sent by the monitoring module, and counts according to the situation of changing lines with the same bank. The present invention avoids the frequent behavior of changing lines in the same bank due to the strong randomness of received commands in the entire DDR system, effectively reduces the behavior of changing lines in the same bank, thereby improving the utilization rate of the DDR bus and improving the access efficiency of the DDR.

Description

technical field [0001] The invention relates to the technical field of storage devices, in particular to a feedback device and method for improving the utilization rate of a DDR bus. Background technique [0002] In DDR memory (dual-channel dynamic random access memory), when a newline command of the same bank (storage bank) appears, it is necessary to wait for a delay time of at least tRC after the first active activation time before the Bank can be used again. The different lines of the active activation operation. [0003] In a general DDR (dual-channel dynamic random access memory) controller, there will be a certain amount of Buffer (cache) depth to store the read and write commands sent by the front-end module. This certain amount is usually selected as an integer power of 2, but at the same time It is necessary to consider the power consumption and area of ​​the chip, and the general Buffer (cache) depth will be 8-16. [0004] At present, the controller command sequ...

AI Technical Summary

Problems solved by technology

[0005] When the same bank line break occurs as described before, there will be a delay time of at least tRC when the bus is empty, so the number of effective commands on the bus will be very low and the situation will be empty waiting for tRC.

This results in low bus utilization and waste of DDR storage bandwidth.

Images