Erase method for flash memory

Abstract

A method for erasing a flash memory is illustrated as follows, wherein the flash memory includes at least one storage block, and the storage block is divided into a plurality of storage segments. Verifying whether a memory block or a memory block corresponding to an address has at least one under-erased transistor memory cell according to a sector enable signal, wherein the sector enable signal depends on whether the memory block has at least one over-erased transistor memory cell unit is determined. If the storage block or storage segment corresponding to the address has transistor memory cells that are insufficient to be erased, the transistor storage cells of the storage block or storage segment are erased according to the segment enable signal.

Description

technical field [0001] The present invention relates to a flash memory, more particularly to an erasing method for the flash memory. Background technique [0002] Flash memory includes a plurality of individual metal oxide semiconductor (MOS) field effect transistor memory cells, each transistor memory cell including a source, a drain, a floating gate, and a control gate. Various voltages can be applied to the above-mentioned plurality of electrodes of the transistor memory cell to program (that is, write) the transistor memory cell into binary 1 or 0, erase all transistor memory cells as a memory block, and read transistor memory cells. memory cells, verify that the transistor memory cells are erased, or verify that the transistor memory cells are not over-erased. [0003] The adverse effect of the leakage current of an over-erased transistor memory cell is described as follows. In a typical flash memory, the drains of a large number of transistor memory cells, for exampl...

AI Technical Summary

Problems solved by technology

This known erasure method requires multiple additional tag buffers and consumes more erasure verification time

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