Prefetch cache control method, device, chip and computer-readable storage medium

Abstract

The invention discloses a prefetch cache control method, device, chip and computer-readable storage medium, wherein the method includes obtaining the address of the first instruction group requested by the processor, if the address of the first instruction group is not in In the preset prefetch cache or record cache, the first content corresponding to the address of the first instruction group is obtained in the memory, wherein the first content includes the first instruction group; the prefetch cache The second content of is updated to the record cache, and the second content in the prefetch cache is updated to the first content. A high-efficiency prefetch cache control scheme is implemented, which avoids the need to re-read due to the coverage of loop instructions, and improves the reading efficiency of continuous instructions and loop instructions.

Description

Technical field [0001] The present invention relates to the field of electronic technology, and more particularly to a prefetch caching control method, a device, a chip, and a computer readable storage medium. Background technique [0002] In the existing chip architecture technology solution, most of the non-volatile memory cells are used to store user programs and related application data, where non-volatile components include EEPROM (Electrical EraSable ProgrammableRead Only Memory). Memory), Flash (flash), etc. [0003] In general, the placement position of the non-volatile memory cells mainly has two kinds of plug-in and embed, in which the data interface considering the plug-in storage device is generally serial, the reading rate is slow, so the plug-in Program storage devices need to match relatively complex Cache prefetch units, require more cache units, and use prediction techniques to maintain cache access and priority, low applicability; considering the performance of ...

AI Technical Summary

Problems solved by technology

However, there is a defect in the above scheme. When the next group of prefetched instructions needs to be cached, some loop instructions will be overwritten and need to be re-read, thus affecting the execution efficiency of the loop instructions.

[0005] To sum up, the caching scheme in the prior art still has the problem of low execution efficiency

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