Transmitting circuit based on DDR writing channel

Abstract

The invention discloses a transmitting circuit based on a DDR writing channel. The transmitting circuit based on the DDR writing channel comprises first to seventh registers and first to third clock selectors, respective output ends of the first register and the third register are respectively connected with two input ends of the first clock selector, respective output ends of the second registerand the fourth register are respectively connected with two input ends of the second clock selector, the output end of the first clock selector is connected with the input end of the fifth register, the output end of the second clock selector is connected with the input end of the sixth register, the output end of the sixth register is connected with the input end of the seventh register, and respective output ends of the fifth register and the seventh register are respectively connected with two input ends of the third clock selector. Therefore, the time sequence requirement of the circuit can be reduced, and the time sequence convergence is easier.

Description

technical field [0001] The invention relates to a sending circuit based on a DDR (Double Rate Synchronous Dynamic Random Access Memory) write channel. Background technique [0002] The transmission of the existing DDR write channel generally adopts 2 times the DDR clock to drive the sequential circuit to realize the double-edge validity of the DDR data. Because of the use of 2 times the frequency, the timing requirements of the circuit are very high. DDR is a high-speed interface. Now the main frequency has reached 3200Mpbs (megabits per second), and the clock of DDR PHY (physical layer) is 1600Mhz (megahertz). The higher and higher the frequency, the more difficult it is to do in terms of timing closure. Contents of the invention [0003] The purpose of the present invention is to provide a transmission circuit based on a DDR write channel, which can reduce the timing requirements of the circuit and make timing convergence easier. [0004] The technical scheme for reali...

AI Technical Summary

Problems solved by technology

Because of the use of 2 times the frequency, the timing requirements of the circuit are very high. DDR is a high-speed interface. Now the main frequency has reached 3200Mpbs (megabits per second), and the clock of DDR PHY (physical layer) is 1600Mhz (megahertz). The higher and higher the frequency, the more difficult it is to do in terms of timing closure

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