A mixed management method for processor array local storage

Abstract

The invention provides a processor array local storage hybrid management technique, and belongs to the technical field of computer system structures and processor microstructures. The processor arraylocal storage hybrid management technique comprises the following steps: S1, dividing on-chip local storage (LDM) of each core in an array processor into a first type region, a second type region anda third type region; S2, setting the first type area as a private storage space which is used for storing local private data and is only visible to an application program of the core in specific addressing; S3, setting the second type area as shared data for storing the plurality of cores, and specifically addressing shared storage space visible to the application programs of the plurality of cores; and S4, setting the third-class region as a Cache storage space for mapping to the whole main storage space, and adopting a Cache mode to manage so as to enable the application program of the coreto access the visible Cache storage space to the Cache space. According to the processor array local storage hybrid management technique, application characteristics are flexibly configured, and the actual running performance of the application is efficiently exerted.

Description

technical field [0001] The invention belongs to the technical field of computer architecture and processor microstructure, and relates to a hybrid management method for local storage of a processor array. Background technique [0002] As the number of cores in many-core processors continues to increase and the computing power is greatly improved, the improvement of the memory access capability of the chip is much slower than the improvement of the computing power. The "storage wall" problem has become an important factor restricting the performance of the chip. On-chip storage hierarchy design that deeply matches application features is an important technical approach to alleviate the memory access wall problem. [0003] Efficiently realizing data sharing among the cores of many-core processors is the key to improving the on-chip data multiplexing rate. However, different applications have quite different requirements for on-chip storage, and different shared working set si...

AI Technical Summary

Problems solved by technology

However, different applications have quite different requirements for on-chip storage, and different shared working set sizes and data access mechanisms have a huge impact on application performance.

There is a lack of adaptability in a single processor core data management method

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