Preparation method of through hole structure and preparation method of three-dimensional memory

Abstract

The embodiment of the invention provides a preparation method of a through hole structure. The preparation method comprises the following steps: providing a substrate structure comprising a first stacking layer; etching the first stacking layer to form a first through hole; forming an epitaxial growth layer at the bottom of the first through hole; forming an etching barrier layer in the first through hole, wherein the etching barrier layer at least covers the surface of the epitaxial growth layer; forming a filling structure in the first through hole; forming a second stacking layer on the first stacking layer; etching the second stacking layer to form a second through hole communicated with the first through hole; etching to remove the filling structure in the first through hole; whereinthe etching selection ratio between the material of the etching barrier layer and any one of the following materials meets the etching barrier requirements: the second stacking layer, the filling structure and the oxide layer of the filling structure. In addition, the embodiment of the invention further provides a preparation method of the three-dimensional memory, and the preparation method comprises the steps in the preparation method of the through hole structure.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for preparing a through-hole structure and a method for preparing a three-dimensional memory. Background technique [0002] With the development of technology, the structure of semiconductor devices is constantly updated and changed, and the traditional through-hole structure and its formation process are gradually unable to meet the functional requirements of new devices. For example, for three-dimensional memory devices, especially 3D NAND memory, as people's demand for high storage density increases, the number of stacked layers of devices is increasing; the channel hole (Channel Hole, CH) of three-dimensional memory devices It is usually necessary to etch the stack until the substrate structure is exposed; in this case, the increased number of stacked layers creates higher requirements and challenges for the etching process of CH. In order to deal with this p...

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Problems solved by technology

However, in practical applications, due to process reasons, there are often seams in the filling of the sacrificial material in the lower via hole; in the process of etching the upper via hole and removing the sacrificial material in the lower via hole, due to the Existence, the etching reaction will damage the epitaxial growth layer (Selective Epitaxial Growth, SEG) at the bottom of the via hole, causing SEG damage, which will seriously affect the reliability of the device

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