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Test system and test method

A technology for testing systems and devices under test, applied in software testing/debugging, error detection/correction, instruments, etc., can solve problems such as low board-level testing efficiency, achieve high testing efficiency, and improve testing efficiency

Active Publication Date: 2020-02-28
SHANGHAI SIGRINER STEP ELECTRIC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the embodiments of the present invention is to provide a test system and test method to solve the technical problem of low board-level test efficiency in the prior art

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0020] figure 1 It is a schematic structural diagram of a test system provided by an embodiment of the present invention. Such as figure 1 As shown, the test system includes:

[0021] A first central processing module, a first cache, and a first interface module connected to each other; the first interface module is connected to the device under test;

[0022] The first interface module is configured to read the first data to be tested from the first buffer and send it to the device under test, and receive the second data to be tested from the device under test and cache it in the first cache;

[0023] The first central processing module is configured to determine that the data transmission test of the device under test is successful when the first data to be tested and the second data to be tested meet a preset condition.

[0024] in,

[0025] The device under test is configured to cache the first data to be tested in a local second cache when receiving the first data to...

Embodiment 2

[0067] figure 2 It is a schematic structural diagram of a test platform provided by an embodiment of the present invention. Such as figure 2 As shown, the test platform includes: including the test system and the equipment under test;

[0068] The test system includes: a first central processing module CPM, a first cache, and a first interface module connected to each other; the first interface module is connected to a second interface module of the device under test;

[0069] The device under test includes: a second central processing module CPM, a second cache and a second interface module connected to each other; the second interface module is connected to the first interface module of the device under test.

[0070] Wherein, the first CPM is connected to the host position, receives the command of the host position, configures the preset condition according to the command of the host position and saves it in the first cache, and writes the first data to be tested into t...

Embodiment 3

[0103] image 3 It is a schematic structural diagram of a test platform provided by another embodiment of the present invention.

[0104] Such as image 3 As shown, in this embodiment, on the basis of Embodiment 2, the first cache includes a first read-only memory buffer ROM Buffer and a first random access memory buffer RAM Buffer;

[0105] The first interface module includes: a first output interface, a first input interface, and a first bidirectional interface;

[0106] The second interface module includes: a second output interface, a second input interface, and a second bidirectional interface;

[0107] The first output interface is connected to the second input interface, the first input interface is connected to the second output interface, and the first bidirectional interface is connected to the second bidirectional interface;

[0108] The first data to be tested includes first digital data and first analog data; the second data to be tested includes second digital...

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Abstract

The embodiment of the invention discloses a test system and a test method. The test system comprises a first central processing module, a first cache and a first interface module which are connected with one another; the first interface module is connected with tested equipment; the first interface module is used for reading first to-be-tested data from a first cache, sending the first to-be-tested data to tested equipment, receiving second to-be-tested data from the tested equipment and caching the second to-be-tested data to the first cache; and the first central processing module is used for determining that the data transmission test of the tested equipment is successful when the first to-be-tested data and the second to-be-tested data meet a preset condition. According to the technical scheme provided by the embodiment of the invention, the board-level test efficiency can be improved.

Description

technical field [0001] Embodiments of the present invention relate to the field of board-level testing, and in particular to a testing system and testing method. Background technique [0002] At present, many test systems, especially board-level test systems, need to manually write test programs, test platforms, and devices under test (such as boards under test) when the device under test requires testing of different data to be tested and test conditions, which seriously affects improved test efficiency. In addition, different test programs and test platforms need to be customized and developed for different devices under test, which is time-consuming and laborious, affects reliability, and brings great inconvenience to maintenance. Contents of the invention [0003] The purpose of the embodiments of the present invention is to provide a test system and a test method to solve the technical problem of low board-level test efficiency in the prior art. [0004] In order to...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/36
CPCG06F11/3684G06F11/3688Y02D10/00
Inventor 李兴鹤糜尧杰吴芸刘小红
Owner SHANGHAI SIGRINER STEP ELECTRIC
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