CIS chip detection system and detection method thereof

Abstract

The invention discloses a CIS chip detection system, which comprises a CIS chip, an FPGA and a probe station, and is characterized in that the FPGA is connected with the CIS chip and the probe stationat the same time; image data generated by the CIS chip is transmitted to the FPGA for caching based on a CIS chip clock; the cached image data is transmitted to the probe station based on the probe station clock to test the image data. According to the detection system of the CIS chip and the detection method thereof provided by the invention, image data generated by the CIS chip can be accurately transmitted to the probe station for detection through the cache effect of the FPGA, and therefore the performance of the CIS chip is accurately judged.

Description

technical field [0001] The invention relates to the field of signal processing, in particular to a detection system and a detection method of a CIS chip. Background technique [0002] Before the CIS chip is packaged, it usually needs to be tested. If the test passes, the subsequent packaging work will continue; if the test fails, it indicates that there is a problem with the CIS chip, and further testing or maintenance is required. [0003] In the prior art, ATE probe stations are usually used to detect unpackaged CIS chips. The usual detection methods are as follows: figure 1 As shown, the ATE probe station is directly connected to the pins of the CIS chip for image data acquisition. Since the ATE probe station and the CIS chip have their own clocks, the ATE probe station clock refers to the clock that ATE receives image data, and the CIS chip clock refers to the clock that the CIS chip generates image data or transmits image data. The clock here includes Phase and freque...

AI Technical Summary

Problems solved by technology

Since the ATE probe station and the CIS chip have their own clocks, the ATE probe station clock refers to the clock for ATE to receive image data, and the CIS chip clock refers to the clock for the CIS chip to generate image data or transmit image data. The clock here includes Phase and frequency, it is difficult to set the CIS chip clock and ATE probe station clock to be consistent in the existing technology, even if the frequency of the two is the same, it is difficult to ensure that their phases are the same

When the clock of the ATE probe station is inconsistent with the clock of the CIS chip, the ATE probe station usually collects the image data generated by the CIS chip based on the clock Clk' of the ATE probe station; this clock mismatch will cause the ATE Errors in the data collected by the probe station, resulting in the image data generated by the CIS chip cannot be accurately collected by the ATE probe station, so that the performance of the CIS chip cannot be accurately judged, which misleads the subsequent process

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