Method for improving log block read-write performance of hybrid mapping algorithm

A hybrid mapping and log technology, applied in computing, memory address/allocation/relocation, instrumentation, etc., can solve the problems of wasting 31/32 performance, wasting performance, etc., and achieve the effect of performance optimization and read and write performance improvement

Pending Publication Date: 2020-05-12
成都三零嘉微电子有限公司
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Problems solved by technology

[0016] The mapping method of the above log blocks is as follows image 3 It can be seen from the above description that since NAND Flash writes and reads in units of pages, when the host writes 512B, the written data is actually 16KB, and it takes 1600μs, which is a write amplification effect, wasting 31 / 32 performance
When the host reads 512B, the same read data is 16KB. This is the read amplification effect, which takes 115μs and wastes 31 / 32 of the performance

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  • Method for improving log block read-write performance of hybrid mapping algorithm
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[0040] The present invention will be further described below in conjunction with the accompanying drawings.

[0041] In the present invention, a method is designed, which adjusts the mapping method of the hybrid log block, and adjusts the log block mapping granularity of the hybrid mapping algorithm to 512B of N times, wherein N*512B can be divisible by the page capacity of NAND Flash. The company's L85A is an example, N can be 1, 2, 4, 8, 16, 32, when N is 32, it is the usual mixed mapping. Taking N as 8 as an example, when N is 8, the mapping granularity of the log block is 8x 512B=4KB, and the page capacity of L85A is 16KB, then construct 4 buffers with the same capacity BUFFER, and the mapping relationship is as follows Figure 4 Shown:

[0042] When the host needs to write 4 pieces of 512B data, the improved hybrid mapping algorithm processing flow is as follows:

[0043] (1) Build four 4KB caches, namely BUFFER1, BUFFER2, BUFFER3, BUFFER4;

[0044] (2) Divide the specif...

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Abstract

The invention relates to the field of data reading and writing of NAND Flash memories, and discloses a method for improving the log block read-write performance of a hybrid mapping algorithm. According to the method, the mapping granularity of a log block of an existing hybrid mapping algorithm is adjusted to be N times of 512B, the N * 512B can be divided by the page capacity of the NAND Flash, at the same time, a plurality of buffers are constructed according to the page capacity of the NAND Flash memory, when data is written, the data is written into the NAND Flash memory through the buffers firstly, and when the data is read, the data is imported into the buffers firstly, and then is returned from the buffers. The read-write performance can be improved by adjusting the mapping granularity of the log blocks, the smaller the N is, the more remarkable the performance improvement is, but the subsequent multiplication of the mapping table entries is, so that in the practical application, the relationship between the performance and the mapping table entries can be comprehensively balanced, when a proper N value is taken, the purpose of performance optimization is achieved.

Description

technical field [0001] The invention relates to the field of reading and writing of NAND Flash memory data, in particular to a method for improving the performance of reading and writing log blocks of a hybrid mapping algorithm. Background technique [0002] The vigorous development of the semiconductor industry has led to the emergence of high-performance memory NAND Flash. NAND Flash memory uses semiconductors as storage media and has the advantages of high speed, low energy consumption and shock resistance. It is widely used in portable storage devices such as U disks and SD cards. Among the popular solid-state drives. Although NAND Flash has many advantages, it also has some shortcomings. The biggest disadvantage is that its erasing life is limited, from the original 100,000 erasing life of SLC NAND Flash to 5,000 erasing of MLC NAND Flash The service life of TLC NAND Flash is about 1500 erasing times recently, making the application of NAND Flash rely on the FTL algori...

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Application Information

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IPC IPC(8): G06F16/18G06F12/02G06F12/1009
CPCG06F16/1815G06F12/0246G06F12/1009Y02D10/00
Inventor王志奇何欣霖周道双
Owner成都三零嘉微电子有限公司