Pipelined ADC with at least three sampling channels

Abstract

A pipelined analog-to-digital converter in which at least one stage includes three or more sampling channels. The at least one stage includes an input sampling circuit, a quantization circuit and an amplification circuit. The input sampling circuit includes three or more channels, one of the three channels samples the received analog signal in each cycle. the quantization circuit receives the samples from the input sampling circuit one cycle after the samples are generated such that the quantization circuit receives samples from one of the three or more channels in each cycle, and Each received sample is quantized into one or more bits of the digital word of that sample. The amplifying circuit receives the sample from the input sampling circuit two cycles after the sample is generated and receives the bit corresponding to the sample one cycle after the sample is generated such that the amplifying circuit from one of said three or more channels receives samples and in each cycle receives said corresponding bits (or an analog signal representing those bits) from said quantization circuit and generates an amplified residual from these samples Signal.

Description

technical field [0001] This application relates to pipelined analog-to-digital converters. Background technique [0002] The analog-to-digital converter (analog to digital converter, referred to as ADC) samples the input analog signal at a uniform time interval (that is, the sampling period), and assigns a digital value containing one or more bits to each sample, so that the input Convert the analog signal to digital signal. ADCs can be implemented using a number of different architectures such as but not limited to Flash (also called direct conversion or parallel), successive approximation, ramp comparison, Wilkinson, integrated, incremental encoding (also called back ramp), Sigma- Delta, time interleaved and pipelining. [0003] A pipelined ADC divides the conversion of each sample into multiple low-resolution cascaded stages, where each stage generates one or more bits of the digital value assigned to the sample. For example, an ADC used to generate a 12-bit value for ...

AI Technical Summary

Problems solved by technology

Other suitable ADCs for high-speed applications are time-interleaved ADCs, but time-interleaved ADCs suffer from time-interleaved clutter

Compared with time-interleaved ADCs, pipelined ADCs have higher performance in terms of clutter signals, while traditional pipelined ADCs for high-speed conversion suffer from high power consumption

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