Packaging structure analysis method

An analysis method and packaging structure technology, applied in semiconductor/solid-state device testing/measurement, electrical components, circuits, etc., can solve problems such as failure to perform normal analysis and difficulty in analyzing POP products, so as to promote product production capacity and accelerate product possession rate effect

Pending Publication Date: 2020-07-03
HITECH SEMICON WUXI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] The main packaging structure of POP products is mainly stacking. The existing analysis method is only for a simple single-layer structure. The internal line unit of the product is relatively simple. There are many difficulties in analyzing POP products when DC Fail occurs using the existing methods.
Conventional analysis methods cannot perform normal analysis, so it is necessary to develop new analysis methods

Method used

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Embodiment Construction

[0012] The utility model is described in detail below, and the description in this part is only exemplary and explanatory, and should not have any limiting effect on the protection scope of the present invention.

[0013] The present invention provides a package structure analysis method, comprising the following steps:

[0014] S1: First place the sample face-to-face for inspection according to the previous method;

[0015] S2: Place the sample vertically to check the circuit between the chip layer and the layer;

[0016] S3: Mark the problematic parts with gold wire;

[0017] S4: Use acid solution for soaking to expose the problem area;

[0018] S5: Final confirmation of placement and SEM, and photo retention.

[0019] It should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner" and "outer" are The orientations or positional relationships shown are only for the con...

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Abstract

A purpose of the invention is to provide a packaging structure analysis method. The packaging structure analysis method comprises the following steps of S1, placing a sample according to a previous mode surface, and checking; S2, vertically placing the sample, and checking the circuits between the layers of the chip; S3, marking a defective part with a gold wire; S4, soaking by using an acid liquor, so that the defective part is exposed; and S5, placing in an SEM, carrying out final confirmation, and keeping the photo. According to the invention, the problem that the short-circuited part of the internal circuit of the chip cannot be found by the conventional method is solved, the defects of circuits existing in the chip are well found, the DC defects are promoted to be improved quickly, the production capacity of Hitech products is promoted, the occupancy rate of high-end market products is increased, and the requirements of Hitech for company planning developed to advanced DRAM at present are met.

Description

technical field [0001] The invention belongs to the field of semiconductor packaging, in particular to a packaging structure analysis method. Background technique [0002] As the most advanced product in the current DRAM market, POP products are ahead of many other products in the industry in terms of structure and technology. The main packaging structure of the product is formed by stacking several chips, and the internal circuit unit is several times larger than that of BOC. This product is mainly used for Mobile DRAM, the market demand is huge, and the product profit is relatively high. [0003] The main packaging structure of POP products is mainly stacking. The existing analysis method is only for a simple single-layer structure. The internal line unit of the product is relatively simple. There are many difficulties in analyzing the DC Fail of POP products with the existing methods. Conventional analysis methods cannot perform normal analysis, so it is necessary to de...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/66
CPCH01L22/14
Inventor 李浩
Owner HITECH SEMICON WUXI
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