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Method for forming stepped structure and related stepped structure and semiconductor device structure

A ladder structure, semiconductor technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as unreliable landing and failure of contact structures

Active Publication Date: 2021-10-26
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the amount of time and other conditions of the etching process increase the likelihood that openings to shallow conductive structures will be overetched (eg, punched through) into underlying conductive structures
Contact structures subsequently formed in such openings do not land reliably on conductive structures, which causes failure of devices containing stepped structures

Method used

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  • Method for forming stepped structure and related stepped structure and semiconductor device structure
  • Method for forming stepped structure and related stepped structure and semiconductor device structure
  • Method for forming stepped structure and related stepped structure and semiconductor device structure

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0079] Embodiment 1. A method of forming a stepped structure, the method comprising: forming a patterned hard mask over a layer; removing an exposed portion of an uppermost sub-layer to form an uppermost portion in the uppermost sub-layer a step; forming a first liner material over the patterned hard mask and the uppermost partial layer; removing a portion of the first liner material to form a layer over the patterned hard mask and forming a first liner on the sidewall of the uppermost sub-layer and exposing the lower layer; removing the exposed portion of the lower layer to form a lower step in the lower layer; forming a second liner material over the hardmask, the first liner, and the underlying layer; removing a portion of the second liner material so that the first liner and the A second liner is formed on the sidewall of the underlying layer and another underlying layer is exposed; the exposed portion of the other underlying layer is removed to form another underlying lay...

Embodiment 2

[0080] Embodiment 2. The method of embodiment 1, wherein removing an exposed portion of an uppermost sublayer to form an uppermost step comprises forming an opening in the uppermost sublayer, the opening comprising a widest opening dimension of the stepped structure .

Embodiment 3

[0081] Embodiment 3. The method of embodiment 1, wherein forming a first liner material over the patterned hard mask and the uppermost sub-layer comprises a step width equal to that of the underlying step A corresponding thickness forms the first lining material.

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PUM

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Abstract

The present application relates to methods of forming stepped structures and related stepped structures and semiconductor device structures. The method includes forming a patterned hard mask over the layer. The exposed portion of the uppermost sub-layer is removed to form the uppermost step. A first liner material is formed over the patterned hard mask and the uppermost partial layer, and a portion of the first liner material is removed to form a first liner and expose an underlying layer. The exposed portion of the underlying stratum is removed to form an underlying step in the underlying stratum. A second liner material is formed over the patterned hard mask, the first liner, and the second liner. A portion of the second liner material is removed to form a second liner and expose another underlying layer. The exposed portion of the other underlying layer is removed to form another underlying step. The patterned hard mask is removed. A stepped structure and a semiconductor device structure are also disclosed.

Description

[0001] priority claim [0002] This application was filed on December 14, 2018, and the designated country is China, and the international patent application PCT / US2018 / 065638 published as International Patent Publication WO 2019 / 133289 A1 on July 4, 2019 entered the national phase, so The above-mentioned international patent application claims the benefit under Section 8 of the Patent Cooperation Treaty of U.S. Patent Application Serial No. 15 / 858,072, filed December 29, 2017. technical field [0003] Embodiments disclosed herein relate to semiconductor fabrication including methods of forming a stepped structure of a semiconductor device structure. More specifically, embodiments of the present disclosure relate to methods of forming a stepped structure having improved step edge placement of the stepped structure, improved step landing placement uniformity, and improved step formation control, and related The ladder structure and semiconductor device structure. Background...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L23/522H01L23/528H01L27/11556H01L27/11582
CPCH10B41/50H10B43/50H10B41/27H10B43/27H01L21/76816H01L21/76877H01L23/5226H01L23/5283H10B43/35
Inventor L·威廉森A·L·奥尔森K·贾殷R·登比W·R·布朗
Owner MICRON TECH INC