A Calibration Method Applicable to Two-step ADC

Abstract

A correction method suitable for a two-step ADC. When the two-step ADC performs normal quantization, first correct the offset of the clamping operational amplifier of the fine slope to eliminate the influence of the offset on the linearity; then use the fine slope to correct the step of the thick slope The slope and weight value of the voltage, by delaying the time when the third switch is turned off after the quantization of the rough ramp, makes the rough ramp continue to rise after the quantization ends, making the voltage loaded on the capacitor approach the ideal voltage, and further quantify the load on the thick ramp. The actual voltage weight on the capacitor uses the thick slope to delay the corresponding number of cycles to compensate for the voltage attenuation caused by factors such as capacitor parasitics, thereby greatly improving the linearity of the system and improving the accuracy of the ADC; Delay processing on some thick slopes does not introduce additional analog devices and does not have a large impact on the overall circuit area.

Description

technical field [0001] The invention belongs to the technical field of analog-to-digital conversion, and in particular relates to a correction method suitable for a two-step ADC. Background technique [0002] With the rapid development of the field of integrated circuits, the integration of integrated circuits is getting higher and higher, requiring higher precision and higher density for circuit design. In the communication industry, under the background of continuous attention and rapid development in the field of image processing and environmental monitoring, the analog-to-digital converter (ADC) as the interface for converting digital information and analog information has become particularly important. This requires the analog-to-digital converter to achieve higher speed and achieve higher precision. In the actual analog-to-digital converter circuit, in addition to requiring as low power consumption as possible, low integral nonlinearity (INL), low differential nonline...

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Problems solved by technology

as attached figure 2 Shown is a schematic diagram of the comparison between the ideally loaded rough ramp step voltage and the actually loaded rough ramp step voltage, where V FB , V FT In order to generate the minimum value and maximum value of the rough ramp voltage, it is the quantization range of the rough ramp. With the continuous increase of the rough ramp voltage code value, the voltage actually loaded on the capacitor after the rough quantization is greatly reduced, and the overall linearity is seriously affected. influences

Further consideration, when the code value is large, the gap between the voltage loaded on the capacitor and the ideal situation is above the 1LSB voltage of the thick slope, resulting in insufficient quantization interval of the fine slope to complete the quantization, which seriously affects the overall accuracy

[0017] It can be seen that due to the nonlinear parasitic capacitance of the device and the influence of switch charge injection in the two-step single-slope ADC, there will be a large gap between the actual quantized output result and the theoretical design value, which will affect the correctness of the quantized result, and ultimately make the analog-to-digital conversion Various performance indicators of the converter are difficult to meet the requirements, including integral nonlinearity (INL), differential nonlinearity (DNL), spurious-free dynamic range (SFDR), etc.

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