Clock fractional divider module, image and/or video processing module, and apparatus

Abstract

The present invention concerns a clock fractional divider module (100) which is formed as, comprises or has integrated therein a dual-core lock step unit (10; 20; 30), wherein said dual-core lock stepunit (10; 20; 30) is configured in order to realize a clock fractional division means, mechanism or process accompanied by an error detection, recognition and / or correction means, mechanism or process.

Description

technical field [0001] The invention relates to a clock fractional frequency divider module, an image and / or video processing module and a device, in particular a vehicle. Background technique [0002] In view of hardware design complexity, cost, and power consumption constraints, in many technical fields involving integrated circuit design, clock fractional divider modules are involved to build compliance to required system processing performance. In such architectures, however, the handling of errors or failures, which are common causes of primary system failures, is often still not entirely satisfactory. Contents of the invention [0003] The fractional clock divider module according to the invention has the advantage of more reliable detection, identification and / or correction of possible errors. This is achieved by providing a fractional clock divider module formed as, including and / or integrated with a dual-core lockstep unit, wherein the dual-core lockstep unit is ...

AI Technical Summary

Problems solved by technology

However, in such architectures, the handling of errors or failures, which are common causes of primary system failures, is often still not entirely satisfactory

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