Failure analysis sample preparation method and failure analysis sample

Abstract

The invention provides a method for preparing a failure analysis sample and a failure analysis sample. The preparation method includes the following steps: providing a stacked package to be analyzed, wherein a plurality of stacked bare chips are arranged in the stacked package, and each bare chip has an The front side of the pad and the back side opposite the front side, the back side of the die is in contact with the front side of its adjacent die, and the pads of the die are electrically connected to the pads of the adjacent die; remove other die until the pads of the die adjacent to the target die are exposed; the exposed pads are electrically drawn out to form a sample for failure analysis. The advantage of the present invention is that the removal operation is performed on the back of the target die, and the non-target die pad is used as an electrical connection, thereby avoiding the removal operation on the front side of the target die with circuit devices, protecting the front circuit devices, and being able to A complete and non-damaged target die is prepared, which greatly improves the success rate of sample preparation and greatly reduces the difficulty of sample preparation.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a method for preparing a failure analysis sample and the failure analysis sample. Background technique [0002] With the rapid development of integrated circuit manufacturing technology, the feature size of semiconductor devices continues to decrease, while the degree of integration continues to increase. Usually, in order to obtain a large-capacity memory chip, it is necessary to stack and package multiple memory dies in the same chip, up to 16 at present. The more dies in a stacked package, the thinner each die needs to be thinned. For failure analysis, it is often necessary to obtain the target single faulty die from multiple stacked dies for dynamic hotspot (dynamic hotspot) analysis. For stacked packages, the processing of samples with thin single die is extremely difficult. [0003] Therefore, how to reduce the difficulty of sample preparation and improve the success r...

AI Technical Summary

Problems solved by technology

For failure analysis, it is often necessary to obtain a target single faulty die from multiple stacked dies for dynamic hotspot analysis, which requires that the taken out target die be intact and free of damage, and be able to perform a complete electrical test. For stacked packages, and single die thinner samples are extremely difficult to handle

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