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Chip-on-film packaging structure

A thin-film-on-chip packaging, thin-film technology, applied in electrical components, electrical solid-state devices, circuits, etc., can solve problems such as large film area

Inactive Publication Date: 2020-10-23
CHIPMOS TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The above-mentioned one-to-one configuration requires a large number of conductive through-holes, takes up a large area of ​​the film, and still restricts the pin layout to a certain extent, so the number of pins, the number of bumps and the The demand for fine spacing still needs to be further improved to meet the design requirements

Method used

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Examples

Experimental program
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Effect test

Embodiment Construction

[0051] Figure 1A is a schematic top view of a chip-on-film packaging structure according to an embodiment of the present invention. Figure 1B yes Figure 1A Schematic bottom view of the thin film chip-on-chip packaging structure. Figure 1C yes Figure 1A An enlarged schematic view of region A of . Figure 1D yes Figure 1B An enlarged schematic view of region B of . Figure 1E yes Figure 1C Schematic cross-sectional view along section line E-E'. Figure 1F yes Figure 1A An enlarged schematic view of region F of . In order to clearly show the connection relationship between the chip 160 and the first upper pin 140, Figure 1A The chip 160 is rendered in perspective.

[0052] Please refer to Figure 1A to Figure 1F , in this embodiment, the film-on-chip packaging structure 100 includes a flexible film 110 , at least two conductive elements 120 , an insulator 130 , at least two first upper leads 140 , at least two lower leads 150 and a chip 160 . The flexible film 110...

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Abstract

The invention provides a chip-on-film packaging structure. The chip-on-film packaging structure comprises a flexible film, at least two conductive members, an insulator, at least two first upper pins,at least two lower pins and a chip. The flexible film is provided with a first surface and a second surface which are opposite to each other, and at least one through hole located in a chip setting area of the first surface. The second surface is provided with a projection area overlapped with the chip setting area. The two conductive members and the insulator are arranged in the through hole, and the two conductive members are separated by the insulator to be electrically separated. The two first upper pins are arranged in the chip setting area and are respectively connected with the two conductive members. The two lower pins extend outwards from the projection area and are electrically connected with the two first upper pins through the two conductive members respectively. The chip is arranged in the chip setting area and comprises at least two first convex blocks; the two first convex blocks are jointed with the two first upper pins.

Description

technical field [0001] The invention relates to a package structure, in particular to a film-on-chip package structure. Background technique [0002] Chip on Film (COF) package structure is a common package type of a driver chip of a liquid crystal display. With the increase in the number of bumps on the chip, the increase in the number of pins and the shrinking of the pitch between the pins, the layout of the bumps and pins is increasingly limited. If the layout of the bumps and pins is improper, bridging is likely to occur during the flip-chip bonding process. [0003] At present, the technology of double-sided circuit film has been proposed, which uses a one-to-one configuration to electrically connect the upper pins on the upper surface of the film and the lower pins on the lower surface of the film through a corresponding number of conductive through holes. Accordingly, the layout flexibility of bumps and pins is improved. The above-mentioned one-to-one configuration...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498
CPCH01L23/49827H01L23/49838H01L23/4985
Inventor 林士熙
Owner CHIPMOS TECH INC
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