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Method and application for performing multiple few-bit addition in parallel by using multi-bit adder

An adder and less-bit technology, applied in instruments, electrical digital data processing, digital data processing components, etc., can solve the problem of underutilized computing power, improve hardware utilization and computing power, and reduce chips Area, the effect of reducing the calculation cycle

Active Publication Date: 2020-10-30
MOLCHIP TECH (SHANGHAI) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

At the same time, we can find that the computing power of the current 128 16-bit binary adders is not fully utilized when performing the calculation of scenario 2

Method used

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  • Method and application for performing multiple few-bit addition in parallel by using multi-bit adder
  • Method and application for performing multiple few-bit addition in parallel by using multi-bit adder
  • Method and application for performing multiple few-bit addition in parallel by using multi-bit adder

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Embodiment

[0031] A method for carrying out a plurality of few-bit additions in parallel with a multi-bit adder, comprising the steps:

[0032] For an N-input multi-bit adder, where N is a natural number greater than 2, the designated bit of each input can be set to 0 to divide the multi-bit adder into a plurality of few-bit adders.

[0033] Then, the multi-bit-less adders formed by division can be used to perform the bit-less addition in parallel.

[0034] see figure 1 As shown, for the multi-bit adder, after division, n few bit adders are formed, which are respectively the few-bit adder 1, the few-bit adder 2, the few-bit adder 3, ..., the few-bit adder n , the divided n few-bit adders can perform multiple few-bit addition operations in parallel, such as performing a1-bit addition operations, a2-bit addition operations, and an-bit addition operations in parallel.

[0035] In this way, by dividing the multi-bit adder into multiple small-bit adders to realize the parallel execution of ...

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Abstract

The invention discloses a method for performing multiple few-bit addition in parallel by using a multi-bit adder and application, and relates to the technical field of data processing. According to the method for performing multiple few-bit addition in parallel by using a multi-bit adder, the method comprises the steps of for an N-input multi-bit adder, setting a specified bit of each input to be0 so as to divide the multi-bit adder into a plurality of few-bit adders, and performing few-bit addition in parallel by using the plurality of few-bit adders formed by division, N being a natural number greater than 2. According to the invention, the multi-bit adder can be used for carrying out multiple few-bit addition in parallel so as to reduce the calculation period, extra hardware does not need to be added, and the hardware utilization rate and the calculation power of the chip can be effectively improved.

Description

technical field [0001] The invention relates to the technical field of data processing. Background technique [0002] The running speed of the computer is getting faster and faster, and it needs to be supported by higher-speed computing circuits. As the main part of the computer, the adder is very important to increase its running speed. [0003] In chip design, different application scenarios such as image processing, video codec, artificial intelligence, and central processing unit design are usually involved. The data volume and data bit width dynamic range corresponding to the peak value of different application scenarios are very large, and hardware design must support Maximum data bit width and real-time processing of peak data. As an example and not a limitation, for example, a 16-bit adder is set in the hardware of a certain application. In the prior art, the 16-bit adder can only add a set of numbers in one cycle, which can be a set of The addition of two 16-bit n...

Claims

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Application Information

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IPC IPC(8): G06F7/505
CPCG06F7/505Y02D10/00
Inventor 谢峥
Owner MOLCHIP TECH (SHANGHAI) CO LTD