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Method for identifying feature graphs of layouts

A technology of feature patterns and identification methods, applied in the field of semiconductors, can solve problems such as inability to implement process requirements well, complex and changeable shapes, and inability to effectively define feature patterns, etc.

Pending Publication Date: 2020-11-17
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

As the technology node of the chip enters tens of nanometers, OPC technology has been widely used. At the same time, the complexity of layout design and the gradual reduction of line width make the optical correction program more and more complicated.
[0003] The feature patterns in the logic area of ​​the metal layer layout are dense and complex and changeable. When the feature patterns in the logic area need to be specially processed due to process requirements, the efficiency of selecting feature patterns is too low, and certain types of feature patterns cannot be effectively defined. The characteristics lead to the inability to better realize the process requirements

Method used

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  • Method for identifying feature graphs of layouts
  • Method for identifying feature graphs of layouts
  • Method for identifying feature graphs of layouts

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Embodiment Construction

[0025] The specific implementation manner of the present invention will be described in more detail below with reference to schematic diagrams. The advantages and features of the present invention will be more apparent from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0026] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements, and are not necessarily used to describe a specific order or chronological order. It is to be understood that these terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein includes a series of steps, the order in which these steps are presented is not necessarily the only order in which these steps can be performed, and some described steps may be omitted and / or...

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Abstract

The invention provides a method for identifying a feature graph of a layout, which is used for identifying the feature graph of OPC (Optical Proximity Correction) processing and comprises the following steps of: checking an OPC early warning position on the layout; dividing a certain range taking the OPC early warning position as the center as a limited range; and extracting the feature graph falling into the limited range. The efficiency of selecting the feature graphs can be improved, and the wanted feature graphs can be better selected.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for identifying characteristic patterns of a layout. Background technique [0002] In the photolithography process, due to the Optical Proximity Effect (Optical Proximity Effect), the actual pattern on the wafer after the design pattern is exposed will be slightly different from the original design, so the optical correction technology (Optical Proximity Correct, OPC) is introduced. An error due to the finite resolution of an optical system. As the technology node of the chip enters tens of nanometers, OPC technology has been widely used. At the same time, the complexity of layout design and the gradual reduction of line width make the optical correction program more and more complicated. [0003] The feature patterns in the logic area of ​​the metal layer layout are dense and complex and changeable. When the feature patterns in the logic area need to be speciall...

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Application Information

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IPC IPC(8): G03F1/36
CPCG03F1/36
Inventor 齐雪蕊孟鸿林胡青张辰明魏芳朱骏
Owner SHANGHAI HUALI MICROELECTRONICS CORP