Mixed-order finite element method and device for triangular prism meshing of integrated circuits

Abstract

The invention provides a mixed-order finite element method and device for triangular prism grid division of integrated circuits: collecting and setting the layer information of polygons in the layout of integrated circuits, projecting the polygons to the same layer and performing initial grid division; simplification and alignment Integrated circuit layout polygons, triangular mesh division and adaptive subdivision of integrated circuit layout polygons from the xy direction; the triangular mesh is expanded into a triangular prism mesh in the thickness direction, and the triangular prism mesh is self-adapted from the z direction Subdivision; use consistent subdivision rules to realize the subdivision of triangular prism grids to tetrahedral grids, and solve the initial value of the electromagnetic field of 3D VLSI based on tetrahedral grids. According to the change speed of the initial value of the electromagnetic field exceeds or does not exceed the preset The tetrahedral mesh of the set value and the tetrahedral mesh of the small-scale area of ​​the integrated circuit layout are used to establish mixed-order elements to realize the mixed-order finite element technology. Realize fast and high-quality triangular prism meshing; improve the calculation accuracy of electromagnetic response.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a mixed-order finite element method and device for triangular prism grid division of integrated circuits. Background technique [0002] With the rapid development of the integrated circuit industry, the traditional two-dimensional packaging technology has been unable to meet the increasing requirements of chip performance and packaging density, and three-dimensional packaging technology has become an irreversible trend of high-density chip packaging. A three-dimensional integrated circuit is to stack multiple planar chips vertically and interconnect them using gold wire bonding or other methods to form a three-dimensional packaging structure. Since the three-dimensional technology makes the most possible use of the three-dimensional space of the chip, more transistors can be packaged in a unit area in the form of stacking, which effectively reduces the delay and power...

AI Technical Summary

Problems solved by technology

However, for a VLSI with a three-dimensional multi-scale structure, the grid refinement usually leads to an abnormal increase of the grid density in a large number of small-scale areas. The effect of increasing the calculation accuracy leads to low calculation efficiency; at the same time, due to the abnormal increase of the grid density in a large number of areas due to grid refinement, the overall number of grids has increased by tens of millions, which poses a challenge to the solution of the sparse matrix

Therefore, for 3D VLSI electromagnetic simulation, it is often used to increase the order of finite elements to improve calculation accuracy, such as increasing the first-order elements to second-order elements, but if all elements are increased to second-order elements, it will also lead to The unknown quantity of calculation increases sharply, but the calculation efficiency is still very low

In order to avoid raising all the units to the second-order unit and causing a sharp increase in the unknown quantity of calculation, it is proposed to use mixed-order finite elements. Based on the posterior error estimation, the second-order unit is used for the area with large error, and the first-order unit is used for other places. The area adjacent to the first-order unit and the second-order unit adopts a transition unit, but for the triangular prism unit, there is still no way to realize the transition unit

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