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Forming method of semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve problems such as the inability to effectively obtain the etching rate, the stoppage of the etching machine, and the failure of the thickness of the gate insulating layer to reach the target thickness, etc.

Active Publication Date: 2021-02-05
晶芯成(北京)科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to provide a method for forming a semiconductor device to solve the problem that the existing method for forming a semiconductor device cannot effectively obtain the etching rate, resulting in the problem that the thickness of the gate insulating layer cannot reach the target thickness
[0006] Another object of the present invention is to solve the problem that the etching machine needs to be stopped when adjusting the etching time of the gate oxide layer in the existing method for forming a semiconductor device.

Method used

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  • Forming method of semiconductor device
  • Forming method of semiconductor device
  • Forming method of semiconductor device

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Embodiment Construction

[0021] The method for forming a semiconductor device proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention.

[0022] Please refer to figure 1 , which is a schematic flowchart of a method for forming a semiconductor device provided by an embodiment of the present invention. Such as figure 1 As shown, the forming method of the semiconductor device includes: Step S1: providing a semiconductor substrate, the semiconductor substrate includes a high-voltage device region and a low-voltage device region, and a first gate insulating layer and a covering layer are formed on the...

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Abstract

The invention provides a forming method of a semiconductor device. According to the method, the etching time of a first etching process is firstly obtained, and the etching rate is accurately obtainedaccording to the etching time of the first etching process and the total thickness of a second gate insulating layer and a side wall layer positioned on the second gate insulating layer; therefore, the etching rate of the etching machine can be tested without shutdown, the etching time of the second etching process can be effectively obtained according to the etching rate and the thickness of thepart, needing to be removed, in the remaining first gate insulating layer, and when the second etching process is executed, the etching time of the second etching process can be accurately controlled, and the thickness of the first gate insulating layer can be reduced to the target thickness, and the performance of the device is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] Semiconductor devices such as Metal-Oxide-Semiconductor Field-Effect Transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) generally include a substrate, a gate on the substrate, and a gate between the gate and the substrate. The gate insulating layer, and the gate spacer located on the sidewall of the gate, wherein the gate insulating layer can isolate the gate from the substrate, and the spacer can protect the gate on the one hand , On the other hand, it can prevent the large dose of source and drain implants from being too close to the conductive channel so that the conduction between source and drain may occur. Usually, there is a certain requirement on the thickness of the gate insulating layer, so that the gate insulating layer has good isolation performance. I...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8234H01L21/66
CPCH01L21/823462H01L22/12H01L22/20
Inventor 李孙峰王嘉祥
Owner 晶芯成(北京)科技有限公司