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Method of forming semiconductor device

A semiconductor and device technology, applied in the field of semiconductor device formation, can solve problems such as the inability to effectively obtain the etching rate, the stoppage of the etching machine, and the failure of the thickness of the gate insulating layer to reach the target thickness, etc.

Active Publication Date: 2021-04-02
晶芯成(北京)科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present invention is to provide a method for forming a semiconductor device to solve the problem that the existing method for forming a semiconductor device cannot effectively obtain the etching rate, resulting in the problem that the thickness of the gate insulating layer cannot reach the target thickness
[0006] Another object of the present invention is to solve the problem that the etching machine needs to be stopped when adjusting the etching time of the gate oxide layer in the existing method for forming a semiconductor device.

Method used

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  • Method of forming semiconductor device
  • Method of forming semiconductor device
  • Method of forming semiconductor device

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Embodiment Construction

[0021] The method for forming a semiconductor device proposed by the present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that, the accompanying drawings are all in a very simplified form and in inaccurate scales, and are only used to facilitate and clearly assist the purpose of explaining the embodiments of the present invention.

[0022] Please refer to figure 1 , which is a schematic flowchart of a method for forming a semiconductor device provided by an embodiment of the present invention. like figure 1 As shown, the method for forming the semiconductor device includes: Step S1: providing a semiconductor substrate, the semiconductor substrate includes a high-voltage device region and a low-voltage device region, and a first gate insulating layer and a cover are formed...

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Abstract

The present invention provides a method for forming a semiconductor device, by first obtaining the etching time of the first etching process, and according to the etching time of the first etching process and the second gate insulating layer and the second gate insulating layer located at the second gate The total thickness of the sidewall layers on the insulating layer can accurately obtain the etching rate, so that there is no need to stop the machine to test the etching rate of the etching machine, and then according to the etching rate and the remaining first gate insulating layer The thickness of the part to be removed can effectively obtain the etching time of the second etching process, thus, when performing the second etching process, the etching time of the second etching process can be accurately controlled, thereby The thickness of the first gate insulating layer can be reduced to the target thickness, thereby improving the performance of the device.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for forming a semiconductor device. Background technique [0002] Semiconductor devices such as Metal-Oxide-Semiconductor Field-Effect Transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET) generally include a substrate, a gate on the substrate, and a gate between the gate and the substrate. The gate insulating layer, and the gate spacer located on the sidewall of the gate, wherein the gate insulating layer can isolate the gate from the substrate, and the spacer can protect the gate on the one hand , On the other hand, it can prevent the large dose of source and drain implants from being too close to the conductive channel so that the conduction between source and drain may occur. Usually, there is a certain requirement on the thickness of the gate insulating layer, so that the gate insulating layer has good isolation performance. I...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/8234H01L21/66
CPCH01L21/823462H01L22/12H01L22/20
Inventor 李孙峰王嘉祥
Owner 晶芯成(北京)科技有限公司