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Non-dominated analog circuit fault parameter range determination method

A technology for simulating circuit faults and determining methods. It is used in analog circuit testing, genetic models, and electronic circuit testing. It can solve problems such as the difficulty of accurate calculation in closed interval analysis and the difficulty in determining the range of fault parameters.

Active Publication Date: 2021-03-09
UNIV OF ELECTRONICS SCI & TECH OF CHINA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

When the circuit structure becomes complex, the analysis of this closed interval will be difficult to calculate accurately, that is, it is difficult to determine the fault parameter range

Method used

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  • Non-dominated analog circuit fault parameter range determination method
  • Non-dominated analog circuit fault parameter range determination method
  • Non-dominated analog circuit fault parameter range determination method

Examples

Experimental program
Comparison scheme
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Embodiment

[0119] In order to better illustrate the technical solutions and technical effects of the present invention, the present invention is experimentally verified using a specific analog circuit. Figure 4 It is a circuit diagram of a second order Thomas analog filter circuit in this embodiment. Such as Figure 4 As shown, the second order Thomas analog filter circuit includes six resistive elements, 2 capacitors, and 3 amplifiers, and the nominal value of each component. figure 2 Scripture. In this embodiment in V out As the measuring point, its transmission function is shown in the following formula:

[0120]

[0121] In this embodiment, the faulty element is set as the resistance R. 3 The value of the parameter is 6kΩ, and the other elements are in the tolerance range (this embodiment sets the tolerance parameter α = 0.05, the tolerance range is (x jN × 95%, x jN × 105%)) The value is randomized. The parameter values ​​of all components are: r 1 = 10058Ω, R 2 = 10012Ω, R 3 = 6000...

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Abstract

The invention discloses a non-dominated analog circuit fault parameter range determination method, which comprises the following steps of: taking an element parameter vector as an individual of a genetic algorithm population, taking a parameter value of a fault element in a preset fault value range when an initial population is generated, taking values of other elements in a tolerance range, and in a genetic algorithm iteration process, during individual optimization, performing individual optimization according to the idea of Pareto optimization, periodically refining the value range of the fault element parameters, and extracting the range of the fault element parameters according to the last generation of population after iteration is completed. The Pareto non-dominated idea is adopted,and the parameter range of the fault element is accurately determined.

Description

Technical field [0001] The present invention belongs to the field of simulation circuit fault diagnosis, and more specifically, involving a method of determining a non-disposable analog circuit fault parameter range. Background technique [0002] In analog circuit operation, component degradation causes performance degradation, timely estimation of component parameters to prevent functional failure. When analog circuit fails, in addition to the faulty element, the faulty component parameter is the random number in the tolerance range, ie all component parameters are variables. The number of simulated integrated circuits is limited, and the number of independent tests is often smaller than the number of components C, so only the debt equation group can only be established by the test amount and component parameters, and the faulty element parameter value cannot be accurately calculated. However, it is possible to obtain a possible fault range according to a circuit structure (tran...

Claims

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Application Information

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IPC IPC(8): G06F30/27G06F30/367G06N3/12G01R31/316
CPCG06F30/27G06F30/367G06N3/126G01R31/316Y04S10/52
Inventor 杨成林龙兵刘震周秀云
Owner UNIV OF ELECTRONICS SCI & TECH OF CHINA