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SOI wafer bonding quality detection method and system

A quality inspection method and wafer bonding technology, applied in semiconductor/solid-state device testing/measurement, electrical components, semiconductor/solid-state device manufacturing, etc., can solve problems such as non-destructive testing of electrical characteristics of bonding interfaces

Inactive Publication Date: 2021-05-07
MICROTERA SEMICON (GUANGZHOU) CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a SOI wafer bonding quality inspection method and system, which is used to solve the problem that the prior art cannot efficiently perform non-destructive inspection on the bonding interface and reveal The problem of its electrical characteristics

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  • SOI wafer bonding quality detection method and system
  • SOI wafer bonding quality detection method and system
  • SOI wafer bonding quality detection method and system

Examples

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Embodiment 1

[0047] see Figure 1 to Figure 17 , the present embodiment provides a SOI wafer bonding quality detection method, characterized in that, comprising the following steps:

[0048] 1) Provide a first wafer 101 and a second wafer 102, the first wafer 101 includes a first silicon layer 101a, a first silicon dioxide layer 101b and a first bonding metal layer 101c stacked in sequence, so The second wafer 102 includes a second silicon layer 102a, a second silicon dioxide layer 102b and a second bonding metal layer 102c stacked in sequence, and the first wafer 101 and the second wafer 102 pass through the The first bonding metal layer 101c and the second bonding metal layer 102c are bonded to each other to form a test structure;

[0049] 2) Performing a capacitive voltage test on the test structure to obtain a capacitive voltage test curve of the test structure, and characterizing the bonding quality of the test structure according to the capacitive voltage test curve.

[0050] In st...

Embodiment 2

[0063] like Figure 2 to Figure 17 As shown, the present embodiment provides a SOI wafer bonding quality detection system, which is characterized in that, comprising:

[0064] Capacitance voltage test module 105, it is used for carrying out capacitance voltage test to test structure; Described test structure comprises the first wafer 101 and the second wafer 102 of mutual bonding, and described first wafer 101 comprises stacked successively The first silicon layer 101a, the first silicon dioxide layer 101b and the first bonding metal layer 101c, the second wafer 102 includes the second silicon layer 102a, the second silicon dioxide layer 102b and the second Bonding metal layer 102c, the first wafer 101 and the second wafer 102 are bonded to each other through the first bonding metal layer 101c and the second bonding metal layer 102c to form the test structure ;

[0065] A data collection and judging module 106, which obtains the capacitance voltage test curve of the test str...

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Abstract

The invention provides an SOI wafer bonding quality detection method and system. The detection method comprises the following steps: providing a first wafer and a second wafer, wherein the first wafer comprises a first silicon layer, a first silicon dioxide layer and a first bonding metal layer which are sequentially stacked, the second wafer comprises a second silicon layer, a second silicon dioxide layer and a second bonding metal layer which are stacked in sequence, and the first wafer and the second wafer are bonded through the first bonding metal layer and the second bonding metal layer to form a test structure; and performing capacitance voltage test on the test structure to obtain a capacitance voltage test curve of the test structure, and representing the bonding quality of the test structure according to the capacitance voltage test curve. Aiming at the quality evaluation requirement of the low-temperature bonding SOI wafer interface, the capacitance voltage test is carried out on the test structure, the rapid and lossless representation of the bonding quality of the SOI wafer is realized, the electrical characteristics of the bonding interface are disclosed, and the method and the system have important significance for the development of a three-dimensional monolithic integration process.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a SOI wafer bonding quality detection method and system. Background technique [0002] With the continuous development of the semiconductor manufacturing process, the feature size of the manufacturing process is continuously reduced, and Moore's Law is approaching the physical limit. In order to further increase the integration level and reduce the interconnection delay, three-dimensional monolithic integration (M3D) has become a new development trend. In the three-dimensional monolithic integration process, the upper-layer devices are manufactured vertically in sequence after the lower-layer devices are manufactured, and the devices of each layer are bonded by wafers through interlayer deposition, and vertically interconnected through holes between monolithic layers. Not only can it significantly reduce interconnection delays and increase chip integ...

Claims

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Application Information

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IPC IPC(8): H01L21/66H01L21/67
CPCH01L21/67253H01L22/12H01L22/14H01L22/20
Inventor 刘海彬刘筱伟胡云斌刘盛富刘森
Owner MICROTERA SEMICON (GUANGZHOU) CO LTD