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Method and system for improving flash simulation accuracy

An accurate and simulated data technology, applied in the field of simulation, it can solve the problems of limited number of read, write and erase operations, high development cost, limited life cycle of NAND Flash, etc.

Active Publication Date: 2021-05-25
YEESTOR MICROELECTRONICS CO LTD
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the storage medium of SSD, NAND Flash generally has a capacity of 128G-1T. The characteristics of Flash determine its limited number of read, write and erase operations, so the life cycle of NAND Flash is also limited. If the real NAND Flash is completely used in the firmware development process It will inevitably lead to high development costs and low efficiency
[0004] At present, the accuracy of the FTL algorithm is verified through simulation, such as reading speed, writing speed, erasing speed, amplification factor, logic data, table data, etc., but simulation is a computer program, and FTL is an embedded program. How to make the simulation The process is close to the accuracy of the chip. For example, the speed of the simulation is consistent with the speed of the real chip, and the number of times of reading, writing and erasing and the amplification factor are the key issues.

Method used

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  • Method and system for improving flash simulation accuracy
  • Method and system for improving flash simulation accuracy
  • Method and system for improving flash simulation accuracy

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Embodiment Construction

[0055] In order to make the purpose, technical solutions and advantages of this application clearer, the following in conjunction with the attached Figure 1-3 And embodiment, this application is described in further detail. It should be understood that the specific embodiments described here are only used to explain the present application, not to limit the present application.

[0056] The embodiment of the present application discloses a method for improving the accuracy of flash simulation. refer to figure 1 , a method for improving the accuracy of flash emulation comprises the following steps:

[0057] S1: Acquire actual parameters of a real chip, where the actual parameters include write speed and read speed.

[0058] S2: Obtain environmental parameters of the simulated device, the environmental parameters include disk write speed and disk read speed.

[0059] S3: Calculate the proportional parameter according to the one-to-one correspondence between the actual param...

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Abstract

The invention relates to the technical field of simulation, in particular to a method and system for improving flash simulation accuracy, and the method comprises the following steps: obtaining actual parameters of a real chip, the actual parameters comprising a writing speed and a reading speed; acquiring environment parameters of the simulation equipment, wherein the environment parameters comprise a disk writing speed and a disk reading speed; calculating proportion parameters according to the one-to-one correspondence of the actual parameters and the environmental parameters; simulating data volume to a simulation program of the simulation equipment through the script to generate simulation parameters; and calculating simulation data according to the simulation parameters and the proportion parameters. The method has the effect of improving the simulation accuracy.

Description

technical field [0001] The present application relates to the technical field of simulation, in particular to a method and system for improving the accuracy of flash simulation. Background technique [0002] The FTL (Flash Translation Layer) algorithm is the core part of the SSD (Solid State Disk) firmware. In order to improve the development and verification efficiency of the FTL algorithm, it is first necessary to have a verification environment. The current firmware verification environment includes SSD master control, NAND Flash particles, DDR, PCIE, DStream and other devices. These hardware products are generally expensive, and some of them are easy to wear and tear. There are also problems of long startup time and poor stability during use. , these factors will directly lead to a reduction in the development efficiency of SSD firmware and an increase in development costs. [0003] In the structure of NAND Flash, DIE is an independently operable unit, which includes mu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F11/34
CPCG06F11/3457Y02D10/00
Inventor 王敏吴大畏罗挺
Owner YEESTOR MICROELECTRONICS CO LTD