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A kind of optimization method of verilog-a model, electronic equipment and computer-readable storage medium
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An optimization method and model technology, applied in computing, software engineering design, electrical digital data processing, etc., can solve problems such as the influence of C++ model codes, and achieve the effect of improving reusability and maintainability
Active Publication Date: 2022-04-08
SHENZHEN HUADA EMPYREAN TECH CO LTD
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In this way, when the Verilog-A model is updated and iterated, even a few changes can have a huge impact on the overall C++ model code
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Embodiment 1
[0023] figure 1 For the optimization method flow chart of Verilog-A model according to the present invention, below will refer to figure 1 , the optimization method of the Verilog-A model of the present invention is described in detail.
[0024] First, in step 101, variables that contribute to the Jacobian matrix are collected, and the variables are globally encoded.
[0025] In the embodiment of the present invention, the variable that contributes to the Jacobian matrix refers to the variable that is related to the port voltage or the port current in the Verilog-A model and contributes to the Jacobian matrix. Contributing variable relationship refers to a hierarchical relationship between the variables assigned and assigned.
[0026] In the embodiment of the present invention, all the variables that contribute to the Jacobian matrix in the traversal module are saved and encoded according to the order in which they are assigned in the module of the Verilog-A model (called gl...
Embodiment 2
[0036] The optimization method of the Verilog-A model of the present invention will be further described below in conjunction with a specific embodiment.
[0037] Traverse all variables that contribute to the Jacobian matrix in the module, save them and encode them in the order in which they are assigned in the module (called global encoding), and add the encoding at the end to ensure that each variable They are all unique, and can also clarify the order in which variables appear. For example, (A,B,C,A,C,D,E,C) is a simple abstract representation of the variable assignment order in a simple module, where (A,B,C,D,E) are five different variables , and encode it according to the global encoding method, it can be expressed as (A1, B2, C3, A4, C5, D6, E7, C8). If the module needs to be iteratively upgraded at this time, and some statements in it need to be adjusted, for example, the B2 variable needs to be deleted now, the module can be expressed as (A1, C2, A3, C4, D5, E6, C7). ...
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Abstract
A method for optimizing a Verilog-A model, an electronic device, and a computer-readable storage medium, the method comprising the steps of: collecting variables that contribute to the Jacobian matrix, and globally encoding the variables; Independent encoding, establish a mapping table from global encoding to independent encoding; optimize variable dependencies; output optimized independently encoded code. The optimization method of the Verilog-A model of the present invention reduces a large number of changes produced when the model is modified by optimizing the code in the module, and improves the reliability of the model while optimizing and accelerating the calculation of the Verilog-A model in the circuit simulator. Reusability and maintainability.
Description
technical field [0001] The invention relates to the technical field of integrated circuitcomputer aided design, in particular to an optimization method for a circuit simulator. Background technique [0002] The Verilog-A language is a high-level language that uses modules to describe the structure and behavior of an analog system and its components. To specify the behavior of individual blocks, the mathematical relationship between their input and output signals needs to be defined. After defining the structure and behavior of the system, the circuit simulator derives a descriptive set of equations from the blocks, solves the system of equations, and obtains the system response. In the process from the device module to the establishment of equations, it is necessary to convert the circuit module built by Verilog-A into a C++ code interface that the circuit simulator can call. [0003] With the rapid iteration of advanced technology, the complexity of device models has inc...
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