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Fractional delay filter design method based on segmented frequency domain optimization

A technology of delay filter and design method, applied in the direction of digital technology network, impedance network, electrical components, etc., can solve the problems of low implementation complexity, consumption of many multipliers and adders, lack of etc., to achieve low implementation complexity , the effect of reducing implementation complexity

Active Publication Date: 2021-06-25
BEIJING INSTITUTE OF TECHNOLOGYGY
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Problems solved by technology

However, whether it is a time-domain design algorithm or a frequency-domain design algorithm, the designed variable fractional delay filter often has high implementation complexity, and will consume a lot of multipliers and adders in actual digital signal processing devices.
[0004] In summary, the existing variable fractional delay filter design methods lack research on low implementation complexity under the condition of meeting the design indicators

Method used

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  • Fractional delay filter design method based on segmented frequency domain optimization
  • Fractional delay filter design method based on segmented frequency domain optimization
  • Fractional delay filter design method based on segmented frequency domain optimization

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Embodiment Construction

[0053] The present invention will be described in detail below with reference to the accompanying drawings and examples.

[0054] In the present invention, the coefficient solution method of the variable fractional delay filter based on segmented frequency domain optimization, such as figure 1 shown, including the following steps:

[0055] Step 1. The design index of the given filter: passband cut-off frequency ω c and the upper limit of design error ε max .

[0056] Step 2. Divide the frequency response of the designed variable fractional delay filter into P sections, then the expression of the frequency response of the i (i=0,1,...,P-1) section is H d (ω,p;i), where ω(ω∈[0,2π]) is the digital frequency. The frequency response H of the i-th segment d (ω,p;i) is decomposed into L(i)+1 sub-filters H(ω,k;i), k is an integer, the value range is k∈[0,L(i)], p is a decimal extension time variable, and p∈[-0.5,0.5]. h d The expression of (ω,p; i) is:

[0057]

[0058] Amo...

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Abstract

Compared with the conventional technology, the variable decimal time-delay filter design method based on segmented frequency domain optimization has the main advantages that the frequency response error function of the variable decimal time-delay filter is segmented, and the filter coefficient is solved independently through second-order cone programming in each segment; and therefore, the designed variable decimal time delay filter has lower implementation complexity under the condition of meeting the requirements of design indexes. According to the method, the joint optimization of the polynomial order and the sub-filter order can be realized, so that the polynomial orders of different segments are different, the sub-filter orders in the same segment are different, and the realization complexity is further reduced.

Description

technical field [0001] The invention belongs to the technical field, and in particular relates to a fractional delay filter design method based on segmented frequency domain optimization. Background technique [0002] In the field of aerospace measurement and control communication, satellite navigation and positioning, the variable decimal delay filter can not only be used in the receiver synchronization algorithm to realize the interpolation and reconstruction of the best sampling point, but also can be used in the channel simulator to realize the digital signal Fractional delay. Therefore, the research on the design method of the variable fractional delay filter has always been one of the hot spots in the field. [0003] The current research on fractional delay filter design methods can be divided into time-domain design algorithms and frequency-domain design algorithms. Time-domain design methods include Lagrangian interpolation design algorithm, Hermitian interpolation...

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Application Information

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IPC IPC(8): H03H17/02
CPCH03H17/0294H03H17/0009
Inventor 王永庆孙杰毅申宇瑶马淑芬陈岩
Owner BEIJING INSTITUTE OF TECHNOLOGYGY
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