High-speed parallel DDC and FIR filtering processing method based on FPGA

Abstract

The invention discloses a high-speed parallel DDC and FIR filtering processing method based on an FPGA. The method comprises the steps of: inputting a signal, and setting the number M of parallel paths according to the data sampling rate of the input signal; then, according to the number M of parallel paths, sampling the input signal in sequence according to every M sampling points and dividing the input signal into M input sub-signals, and then performing digital down-conversion on each input sub-signal to generate a corresponding first intermediate signal and an intermediate signal; and filtering the first intermediate signal or the second intermediate signal through an FIR (Finite Impulse Response) filter to generate four corresponding output sub-signals, wherein the data sampling rate of each output sub-signal and the data sampling rates of the input sub-signal, the first intermediate signal and the second intermediate signal are all 1 / M of the input signal. By designing a parallel architecture, the problem that the FPGA processor cannot process data signals with high-speed data sampling rate is solved.

Description

technical field [0001] The invention relates to signal processing of FPGA processors, in particular to FPGA-based high-speed parallel DDC and FIR filter processing methods. Background technique [0002] The FPGA processor supports full parallel computing and is more suitable for high-speed data signal processing. For FPGA processors, data signals are generally processed in parallel in the form of pipelines, and due to the limitations of the FPGA processor's internal look-up table, routing, multiplier unit delay time, etc., the operating speed of the FPGA processor is usually Between 200M and 300M. Especially for the echo signal of the radar equipment, due to the limitation of the internal hardware of the FPGA processor, it can only process the data signal with a sampling rate of 350MSPS and below. [0003] However, the data sampling rate of the echo signal of the existing radar equipment is generally 480MSPS and above, and the existing FPGA processor cannot process the ech...

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Problems solved by technology

[0004] In order to overcome the deficiencies in the prior art, the object of the present invention is to provide FPGA-based high-speed parallel DDC and FIR filter processing method, which can solve the problem that FPGA processors in the prior art cannot process data signals at high data sampling rates

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