52 results about "Costas loop" patented technology

The invention provides a modulation and demodulation method for direct spread DPSK (Differential Phase Shift Keying) signals, including the following steps: generating a set of 0/1 original data; performing 2/3 convolution encoding and differential encoding on the original data; performing spectrum spreading on the encoded data by using a spread spectrum code; performing subcarrier modulation on the signals after spectrum spreading to obtain direct spread DPSK signals; performing down-conversion and low-pass filtering on the received direct spread DPSK signals, and shifting the frequency spectrum to near the zero frequency; synchronizing (including capturing and tracking) the data after down-conversion, capturing the pseudo code phase difference by matched filtering, and capturing the Doppler frequency offset value by using a multi-delay correlation algorithm, in order to complete a coarse synchronization process; carrying out code tracking through a lead-lag delay phase-locked loop, and carrying out carrier phase tracking through a Costas loop, in order to realize the synchronization of code phase and carrier; and de-spreading and demodulating the synchronized signals to obtain transmission information. The anti-interference ability of signals is improved, the synchronization of a pseudo code and a carrier is realized, and correct de-spreading and demodulating of the receiveris ensured.

The invention provides a 16 quadrature amplitude modulation (QAM) demodulation synchronization method. The method comprises a first step of adding a power detection technology on a traditional costas loop of quadrature phase shift keying (QPSK) so as to finish carrier recovery; a second step of performing matched filtering on each same-phase orthogonal component signal, so as to reduce noise effect and prepare for bit synchronization; a third step of performing bit timing recovery on same-phase orthogonal signals through an "early-late gate"; a fourth step of setting a threshold, and performing sampling judgment and 4-2 level conversion on each of two paths of signal to obtain parallel signals; and a fifth step of performing differential decoding and parallel-serial conversion on the parallel signals, then recovering and obtaining original signals. According to the introduced novel carrier synchronization technology, the carrier recovery is finished by using a phase-locked loop; on the basis of the traditional costas loop, the power detection technology is added, so that the linear output of a phase discriminator is guaranteed, the tracking precision and speed are improved, and the novel carrier synchronization technology passes field programmable gate array (FPGA) hardware verification.

In a receiver, a decision-directed phase estimator is used in conjunction with an interpolator to provide a phase estimate for use in carrier recovery. For example, a receiver comprises a pilot phase estimator, a Costas loop and an interpolation controller. The pilot phase estimator provides determined phase estimates at the pilot times and the interpolation controller provides interpolated phase estimates at other times as a function of a linear interpolation based on a respective determined phase estimate and at least one decision-directed phase error estimate from the Costas loop.

The invention discloses a fast fourier transform (FFT) carrier frequency estimation and Costas loop based non-cooperative communication carrier synchronization system. The system comprises two parts, namely, an FFT carrier frequency estimation module at the front end and a Costas loop carrier synchronization module at the rear end. According a working principle, an input signal simultaneously acts on the two modules; the FFT carrier frequency estimation module firstly performs carrier frequency estimation on the input signal, and an enabling end of the Costas loop is valid till the FFT carrier frequency estimation module transmits estimated carrier frequency to the Costas loop; the carrier frequency is transmitted to a numerically controlled oscillator (NCO) in the Costas loop carrier synchronization module by using an estimation value of the carrier frequency as an initial oscillation frequency; the oscillation frequency of the NCO is controlled, and high-precision carrier synchronization is performed on the input signal; and after capture of the input signal is finished, the NCO outputs a precise carrier extraction signal. According to the system, capture time is shortened, and capture bandwidth is increased indirectly, so that carrier synchronization of an unknown signal in non-cooperative communication is completed.

The invention discloses a multi-rate self-adaptive demodulating system aiming at residual carrier modulation. The system mainly aims at a BPSK modulation mode adopting Manchester encoded residual carrier stated in a CCSDS near linkage standard protocol, the information rate can be estimated in the absence of priori information; and the lox-complexity tracking and demodulating can be realized. Through the fine filtering and narrow-band wide-loop tracking, the extracting and tracking on the carrier are realized; the carrier is locked on an I branch and a signal is locked on a Q branch through the tracking of the Costas Loop; the tap extraction on each rate signal is realized; the matching correlation and the energy integral are performed on the Q branch signals on the rate taps according to the characteristics of the Manchester encoding, thereby judging the rate of the current transmission data through the judgment to the energy integral under the condition of unnecessarily knowing the transmission information, and realizing the self-adaptive demodulation.

The present invention discloses a intermediate frequency demodulator which is suitable for multicode speed and has a plurality of demodulating modes, including: orthogonal tuner, Costas loop, clock and baseband signal treatment circuit, anti-aliasing filter, analog-digital convertor and singlechip; The Costas loop is digital Costas loop; the anti-aliasing filter connects with the outer intermediate frequency filter wherein; the anti-aliasing filter, the analog-digital convertor, the orthogonal tuner, the Costas loop, the clock and the baseband signal treatment circuit connect with each other by electricity in order; the singlechip connects with the orthogonal tuner as well as the Costas loop. The present invention uses the digital orthogonal tuner and digital Costas loop and singlechip to replace analog orthogonal tuner, Costas loop, to implement demodulation of intermediate frequency signal of a plurality of code speed and modulating modes. Compared with the existing intermediate frequency demodulator, the present invention adds flexibility, improves demodulation performance, reduces volume and weight as well as power consumption.

The invention relates to a method and device for decoding time information of a BPL (broadband over power line) receiver. The method is technically characterized by comprising the following steps of: performing 12bit A/D (analog/digital) sampling conversion on a received BPL long wave time service signal, and performing digital filtering and other preprocessing; carrying out carrier removal by using a Costas loop to acquire carrier phase modulation information of the BPL long wave time service signal; performing relevant frequency mixing on the BPL long wave time service signal which is subjected to the sampling and filtering processing; and filtering out a high frequency component by using a FIR (far infrared) low pass filter, sending data to a DSP (digital signal processor) along an I/Q branch, wherein the DSP performs phase verification, loop filtering and other processing mainly according to the data of the I/Q branch so as to control and process a carrier tracking loop. When the method for decoding the time information, provided by the invention is used for encoding the BPL long wave time service signal, the decoding error rate at a signal-to-noise ratio (SNR) of more than or equal to 5dB is more than 0.05 percent, and the timing uncertainty of a 1PPS timing signal generated by the standard time information which is acquired by decoding is less than or equal to 200ns.

The invention discloses a wireless relay transmission realization method based on USRPN200. The method is suitable for multimedia data transmission of different types. This transmission technology hasbeen realized on a USRP platform, the signal processing and the time synchronization is generated in the GNU Radio environment, the resource and power sharing is realized among multiple nodes, the multi-path fading is overcome, and the virtual MIMO is realized. In the indoor environment, the multi-hop network is replaced with the cooperative relaying, the modulation is performed by using Gaussianminimum frequency-shift keying, the network design adopts a decoding forwarding scheme, the frequency phase-locked loop and the Costas loop are used for eliminating the frequency offset and the phasefrequency-shift. The synchronization among multiple relay nodes is realized by using a flow label in the GNU Radio, the transcripts transmitted by multiple relay signals are combined by using equal gain ratio combination at a destination node of the cooperative communication.

The invention refers to an initialization sequence for bi-directional communications in a carrier-based system. A method is provided. An initial bit sequence is received by a receiver. A local oscillator is locked initially to a local reference and subsequently to the received signal using the initial bit sequence, and automatic gain control (AGC) is performed once the local oscillator is locked to the local reference. A Costas loop is then activated so as to achieve carrier frequency offset (CFO) lock, and sign inversion is detected. The receiver then synchronized with an end-of-training pattern.

The utility model discloses a sidetone extraction module, which comprises a phase-locked loop and a digital frequency synthesizer, wherein the phase-locked loop is used for receiving and tracking a sine distance measuring tone signal which is received by a satellite, and obtaining and outputting the frequency and phase of the sine distance measuring tone signal, and the digital frequency synthesizer is connected with the output end of the phase-locked loop through a circuit, and is used for regenerating and outputting the sine distance measuring tone signal according to the outputted frequency and phase of the phase-locked loop. The sidetone extraction module has the advantages that a digital Costas loop with narrow loop bandwidth, small loop noise and high tracking accuracy is used for tracking the sine distance measuring tone signal generated by a ground station to obtain the frequency and phase of the sine distance measuring tone signal, and then the sine distance measuring tone signal is duplicated by the digital frequency synthesizer, and is sent to a downlink link modulator to modulate the phase of a downlink carrier, so the stability is high, the resource consumption is decreased, the system complexity is decreased, and the resource consumption is further decreased; the tracking bandwidth is small, the tracking accuracy is higher, and the high-accuracy forwarding of the distance measuring signal is realized.

The invention requests to realize a variable code rate carrier synchronization structure based on Costas ring, and belongs to the technical field of signal processing. The present invention aims at the defect that the existing Costas ring structure needs to fix the parameter value corresponding to the specific code rate inside the program in advance, and the parameter value cannot be modified in real time. Based on the analysis and research of the original Costas ring structure, a Costas ring carrier synchronization system whose parameters can be modified in real time and whose code rate is variable is designed and implemented. The system uses an external controller to dynamically calculate each parameter according to the change of the code rate, and updates to the Costas carrier synchronization loop in real time with the help of FPGA overload technology. The method can quickly realize the carrier synchronization of the variable code rate in a wide range, so it is of great significance to the subsequent signal processing.

An analogue modem circuit and carrier recovery method are disclosed for use between an RF receiver and a digital modem circuit configured for receiving a baseband RF input signal, and including an up-converter with frequency supplied by an up-converter voltage controlled oscillator, VCO; a down-converter with frequency supplied by a down-converter VCO; a Costas loop sub-module; and baseband outputs from the down-converter to a digital modem circuit. The up-converter feeds the down-converter, and the Costas loop module performs Costas loop functionality on the output of the down-converter to control the up-converter VCO frequency output to thereby control modification of rotation of symbols of the baseband signal.

The invention relates to a CE-OFDM phase demodulation system and method. The CE-OFDM phase demodulation system comprises an input module for inputting a modulation signal in CE-OFDM. A first Costas loop module generates a first original demodulation signal according to the modulation signal. A frequency offset estimation module performs frequency offset estimation on the first original demodulation signal to generate frequency offset information. The phase demodulation module generates a final demodulation signal according to the frequency offset information. According to the invention, crosstalk of adjacent data caused by frequency deviation and even failure to normally decode information can be avoided, the phase demodulation module generates a final demodulation signal according to thefrequency deviation information, and the accuracy of the final demodulation signal is improved.

The invention discloses a satellite-borne low-code-rate BPSK demodulation Costas loop circuit which comprises a multiplier, an active low-pass filter, a voltage-controlled crystal oscillator, a frequency divider, a detector, a comparator and a loop filter and is used for completing demodulation of an extremely-low-code-rate BPSK signal. The circuit is based on a classical Costas ring, wherein thecore circuits are all simulation devices, the phase discriminator is realized by a multiplier, the active low-pass filter is composed of an operational amplifier, the bandwidth of the active low-passfilter is extremely narrow, the voltage-controlled crystal oscillator outputs reference signals to be subjected to frequency division by a frequency divider to obtain BPSK carrier signals, and I-pathsignals and Q-path signals are subjected to phase discrimination by the multiplier and then can obtain locking indication signals through a comparator. Aiming at BPSK signal demodulation with an extremely low code rate, the circuit can provide an excellent demodulation performance and a reliable locking indication signal, meets the use requirements of satellites, and has the advantages of simplicity, reliability, easiness in implementation, low cost, good radiation resistance and the like.

The invention discloses a digital COSTAS loop. The digital COSTAS loop comprises a first phase discriminator, a second phase discriminator, a signal phase-shift module, a voltage controlled oscillator and a loop filter, wherein the output ends of the first phase discriminator and the second phase discriminator are coupled with the input end of the loop filter through a first multiplier, the output end of the loop filter is coupled with the input end of the voltage controlled oscillator, the output end of the voltage controlled oscillator is coupled with the input end of the first phase discriminator through a seocnd multiplier, the output end of the voltage controlled oscillator is also coupled with the input end of the signal phase-shift module, the output end of the signal phase-shift module is coupled with the input end of the second phase discriminator through a third multiplier; and the loop filter contains a PID controller. The digital COSTAS loop has simplified structure, and can demodulate the carrier signal stably and fast.

The invention relates to the technical field of communication and particularly relates to a rapid carrier recovery system and method based on a combined ring. A fast carrier recovery system based on the combined ring comprises a Costas ring, a general carrier recovery ring and a selection switch. The Costas ring and the universal carrier recovery ring form the combined ring. According to the fastcarrier recovery method based on the combined ring, a section of pulse data of which the frame structure consists of a synchronization head and synchronization data is preset. The synchronization headcomprises single carrier data and fixed data. The carrier recovery system combining a Costas loop and a universal carrier recovery loop is used for capturing and tracking pulse data. Carrier recoveryrate is improved, rapid carrier recovery is achieved, it is guaranteed that the frequency deviation after carrier recovery cannot be increased along with increase of the working time, and the requirement for high carrier recovery accuracy in short carrier recovery time is met.

The invention discloses a novel phase discriminator for BPSK signal demodulation. The circuit comprises a phase selector U1, a phase inverter INV1, a switch MUX1 and an exclusive-OR gate XOR1. In a BPSK modulation mode, a phase of a carrier signal is judged to execute the opposition or not according to a baseband signal which is 0 or 1, the phase of a modulating signal can generate 1800 of the mutation, so the BPSK signal phase discrimination can be difficultly realized by a general clock phase discriminator. The circuit has the advantages that the circuit can be directly used for the phase discrimination of the BPSK carrier signal, a general PLL structure can realize the BPSK signal demodulation by using the provided phase discriminator, and complicated demodulation methods, such as a quadratic loop and a Costas loop, are not needed. In addition, the circuit is simple in structure, and easy to integration. The working speed of the circuit can reach more than GHz of the frequency, andthe power consumption is lower, so the novel phase discriminator has the more flexible and extensive application.

A speed sensor including at least one sensor element and an analog-to-digital converter that digitizes the output signals of the at least one sensor element, and a Costas loop unit that is connected to the output of the analog-to-digital converter.