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Power-down protection method for a nonvolatile memory

A power-down protection, non-volatile technology, applied in the direction of instruments, electrical digital data processing, generation of response errors, etc., can solve problems such as low efficiency

Inactive Publication Date: 2021-07-16
XIAN KEYWAY TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the past, the power-down protection of non-volatile memory was implemented by software. The chip needs to execute dozens of CPU instructions to complete a data backup and update, and the execution efficiency is relatively low.

Method used

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Examples

Experimental program
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Effect test

Embodiment Construction

[0015] The non-volatile memory power-down protection method of the present invention will be described in detail below by examples.

[0016] The non-volatile memory power-down protection method of the present invention is Flash in the present embodiment; with an address space of two equally sizes within the flash, respectively, the address space A and an address space A`; the address space A and address space a` There is a backup flag tag and backup number label; the address space A is different from the physical address of the address space A`, the logical address is the same; the address space A and address space A` Range Backup area and target zone; that is, the CPU does not need to know that the data is written in the area A or zone A`, this is all assigned by the flash controller, in this Under operation, region A and region A. Turns as backup zones and target areas, that is, when the CPU is to be updated for the first time, the area A is a backup area and the region A` to do...

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PUM

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Abstract

A power-down protection method for a nonvolatile memory belongs to the field of data power-down protection, and is characterized by comprising the following steps: two address spaces with the same size in the memory, namely an address space A and an address space B are taken; the address space A and the address space B are internally provided with backup mark labels and backup frequency labels; the address space A and the address space A serve as a backup area and a target area in turn; the backup mark label and the backup frequency label are synchronously updated after data storage is finished each time; and after power failure and power-on are carried out again, the two address spaces A are compared with the backup marks and the backup times of the address spaces A, so that the effective address space of the data can be judged, and the power failure protection of the data in the nonvolatile memory is realized. The power failure protection method for the nonvolatile memory not only can ensure that the data of the nonvolatile memory of the security chip is not lost during power failure, but also can improve the data updating performance of the nonvolatile memory.

Description

Technical field [0001] The invention belongs to the field of data power-down protection, and more particularly to a non-volatile memory power-down protection method. Background technique [0002] Non-volatile memory (NVM) has the characteristics of data power-down, so the safety chip usually stores applications, user data, and system files with non-volatile memory. During the operation of the safety chip, if the non-volatile memory is performing erasing or programming operation, the data in the non-volatile memory may be misuse due to some reason. Due to the special application of the safety chip, the key information of the user is stored in the non-volatile memory, and if these critical information is mislead, it may cause huge losses to the user. In order to ensure user information security, the safety chip takes a data power-down protection mechanism to non-volatile memory, which ensures that the safety chip is powered down, and the data stored in the non-volatile memory when ...

Claims

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Application Information

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IPC IPC(8): G06F11/14
CPCG06F11/1441
Inventor 刘升唐伟
Owner XIAN KEYWAY TECH
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