Semiconductor device having stacked structure therein supporting high integration
A technology of stacked structure and semiconductor, applied in the direction of semiconductor devices, electric solid state devices, electrical components, etc.
Pending Publication Date: 2021-08-06
SAMSUNG ELECTRONICS CO LTD
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Problems solved by technology
Forming the upper stack structure on the lower stack structure and forming multiple channel structures extending vertically through the upper stack structure and the lower stack structure may face various technical challenges and limitations
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[0011] figure 1 is a cross-sectional view explaining a semiconductor device according to a disclosed exemplary embodiment. figure 2 is showing figure 1 Enlarged view of part 12 of . image 3 is showing figure 1 Enlarged view of section 13. Figure 4 is showing figure 1 Enlarged view of section 14. Figure 5 to Figure 8 is showing figure 1 Enlarged view of section 13. Figure 9 is showing figure 1 Enlarged view of section 15. Figure 10 is showing figure 1 Enlarged view of section 16. Figure 11 is showing figure 1 Enlarged view of section 17 of . A semiconductor device according to disclosed exemplary embodiments may include a nonvolatile memory such as VNAND or other 3D flash memory. A semiconductor device according to disclosed exemplary embodiments may be construed as including a cell on periphery (COP) structure.
[0012] refer to figure 1 , each of the semiconductor devices according to the disclosed exemplary embodiments may include a substrate 31, an ele...
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A semiconductor device having a stacked structure is provided. The semiconductor device includes an upper stack structure extending over a lower stack structure, the lower stack structure extending over an underlying substrate. A channel structure extends through the upper stack structure and the lower stack structure. The lower stack structure includes a first lower electrode layer disposed adjacent to an interface between the lower stack structure and the upper stack structure, and a second lower electrode layer disposed adjacent to a center of the lower stack structure. The upper stack structure includes a first upper electrode layer disposed adjacent to the interface and a second upper electrode layer disposed adjacent to a center of the upper stack structure. At least one of the first lower electrode layer and the first upper electrode layer is thicker than the second lower electrode layer. At least one insulating layer is disposed between the first lower electrode layer and the first upper electrode layer.
Description
[0001] This patent application claims priority from Korean Patent Application No. 10-2020-0013087 filed on February 4, 2020, the disclosure of which is hereby incorporated by reference. technical field [0002] The disclosed exemplary embodiments relate to a semiconductor memory device using a stack structure and a method of forming the semiconductor memory device. Background technique [0003] In accordance with high integration of semiconductor devices, development of techniques for sequentially stacking a plurality of stacked structures on a substrate is underway. Forming the upper stack structure on the lower stack structure and forming a plurality of channel structures vertically extending through the upper stack structure and the lower stack structure may face various technical challenges and limitations. For example, a device disposed adjacent to an interface between a lower stack structure and an upper stack structure may exhibit various changes in electrical charact...
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IPC IPC(8): H01L27/11582H01L27/1157
CPCH10B43/35H10B43/27H10B43/40H01L29/792H01L29/66833H10B43/50
Inventor 李相在金在炯殷东锡
Owner SAMSUNG ELECTRONICS CO LTD