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Sic semiconductor substrate, method for manufacturing same, and device for manufacturing same

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, chemical instruments and methods, crystal growth, etc., can solve problems such as rough surface of epitaxial layer and deterioration of cut-off characteristics

Pending Publication Date: 2021-08-06
KWANSEI GAKUIN EDUCTIONAL FOUND +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, there is a problem that a part of BPD (for example, at 0.1 to several / cm 2 The density) continues to the problem of epitaxial layer
[0006] However, in Non-Patent Document 1, a problem is pointed out that when epitaxial growth is performed on a surface where pits are formed, the shape of the pits at the time of epitaxial growth is inherited and the surface of the epitaxial layer becomes rough
[0007] Furthermore, it is reported in Non-Patent Document 2 that in such a pn junction diode embedded in an epitaxial layer, by reducing the BPD density, the reliability of the on-state characteristics is definitely improved, but the off-state characteristics are deteriorated on the contrary.

Method used

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  • Sic semiconductor substrate, method for manufacturing same, and device for manufacturing same
  • Sic semiconductor substrate, method for manufacturing same, and device for manufacturing same
  • Sic semiconductor substrate, method for manufacturing same, and device for manufacturing same

Examples

Experimental program
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Effect test

Embodiment 1

[0262] Example 1 uses Si vapor pressure etching to remove the strained layer 11 without forming MSB (strained layer removal step S10), and uses sublimation method to grow under SiC-C equilibrium vapor pressure environment (epitaxial growth step S20). As a result, the BPD conversion rate of growth layer 13 was 100%. At this time, the terrace width W1 before the epitaxial growth step S20 is 14 nm, and the terrace width W2 after the epitaxial growth step S20 is 55 nm (the terrace width increase / decrease rate=292.86%).

Embodiment 2

[0263] Example 2 uses the silicon vapor pressure etching method to remove the strained layer 11 under the condition that the MSB is formed (strained layer removal step S10), and grows under the same conditions as in Example 1 (under the SiC-C equilibrium vapor pressure environment) (Epitaxial growth step S20). As a result, the BPD conversion rate of the growth layer 13 was 99.7%. At this time, the terrace width W1 before the epitaxial growth step S20 is 26 nm, and the terrace width W2 after the epitaxial growth step S20 is 40 nm (the terrace width increase / decrease rate=53.85%).

[0264] Also, from this result, it can be seen that when MSBs are formed on the surface of SiC substrate 10 before epitaxial growth, compared with Example 1, the BPD conversion rate is low.

Embodiment 3

[0265] Example 3 does not perform the strained layer removal step S10 for removing the strained layer 11, and grows under the same conditions as in Examples 1 and 2 (under a SiC-C equilibrium vapor pressure environment) (epitaxial growth step S20) . As a result, the BPD conversion rate of growth layer 13 was 95.65%. At this time, the terrace width W1 before the epitaxial growth step S20 is 7 nm, and the terrace width W2 after the epitaxial growth step S20 is 45 nm (the terrace width increase / decrease rate=542.86%).

[0266] From this result, it can be seen that by including epitaxial growth step S20 for growing SiC substrate 10 under the SiC-C equilibrium vapor pressure environment, the BPD conversion rate of growth layer 13 reaches 95% or more. In addition, it can be seen that when the strained layer 11 remains on the SiC substrate 10 before the epitaxial growth, the BPD conversion rate is low compared with Example 1 and Example 2.

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Abstract

The present invention addresses the problem of providing a SiC semiconductor substrate in which the density of basal plane dislocations (BPD) in a growth layer can be reduced, and a method and device for manufacturing the SiC semiconductor substrate. The present invention is characterized by including a strained-layer removal step S10 for removing a strained layer 11 introduced to the surface of a SiC substrate 10, and an epitaxial growth step S20 for performing growth under a condition in which the terrace width W of the SiC substrate 10 is increased. By manufacturing a SiC semiconductor substrate 14 by these steps, basal plane dislocations BPD in a growth layer 13 can be reduced, and the yield of a SiC semiconductor device can be enhanced.

Description

technical field [0001] The present invention relates to a SiC semiconductor substrate and its manufacturing method and manufacturing device. Background technique [0002] An epitaxial wafer obtained by epitaxially growing SiC on a SiC (silicon carbide) substrate has many crystal defects and dislocations, which adversely affect the characteristics of a SiC semiconductor device. [0003] In particular, a basal plane dislocation (BPD: Basal Plane Dislocation) in a layer obtained by epitaxial growth (hereinafter referred to as an epitaxial layer) propagates into a stacking defect when the SiC semiconductor device is subjected to bipolar operation. Since this stacking defect increases the on-voltage of the SiC semiconductor device and causes bipolar degradation, a technique for reducing BPD in the epitaxial layer is highly desired. [0004] BPD usually hundreds to thousands / cm 2 density exists in the SiC substrate. It is known that most of these BPDs are converted into edge di...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): C30B29/36C30B25/20H01L21/205
CPCC30B25/20C30B29/36C30B23/02H01L21/02378H01L21/02433H01L21/02658H01L21/02631H01L21/02529H01L21/02428H01L21/02612
Inventor 金子忠昭芦田晃嗣井原知也堂岛大地
Owner KWANSEI GAKUIN EDUCTIONAL FOUND