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High bandwidth memory having plural channels

A memory chip and channel technology, applied in the field of high-bandwidth memory with multiple channels, can solve problems such as power potential changes

Pending Publication Date: 2021-08-24
MICRON TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, when accesses are concentrated in the same channel, current consumption is concentrated in the same area of ​​the same memory chip, which may cause a change in power potential

Method used

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  • High bandwidth memory having plural channels
  • High bandwidth memory having plural channels
  • High bandwidth memory having plural channels

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Embodiment Construction

[0034] Various embodiments of the present invention will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, certain aspects and embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. The various embodiments are not necessarily mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0035] figure 1 The semiconductor device 1 shown in has a control chip 20 and four memory chips 10 to 13 stacked on the control chip 20 . The memory chips 10 to 13 are, for example, DRAMs (Dynamic Random Access Memory). Each of...

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Abstract

Disclosed herein is an apparatus that includes: a control chip; a plurality of memory chips stacked on the control drip, the plurality of memory chips including first and second memory chips; and a plurality of via conductors connected between the plurality of memory chips and the control chip. Each of the first and second memory chips is divided into a plurality of channels including a first channel. The plurality of via conductors include a first via conductor electrically connected between the first channel in the first memory chip and tire control drip, and a second via conductor electrically connected between the first channel in the second memory chip and the control chip. The first and second memory drips substantially simultaneously output read data read from the first channel to the first and second via conductors, respectively.

Description

Background technique [0001] A memory device called HBM (High Bandwidth Memory) has a structure in which memory chips each having a plurality of channels are stacked. The channels may operate asynchronously and not exclusively to each other. Since distinct data paths are respectively assigned to channels, HBM can input or output large amounts of data at high speed. [0002] When access to a certain channel in a general HBM is requested from the controller, a memory cell array included in any one of the stacked memory chips is selected. Therefore, when accesses are concentrated in the same channel, current consumption is concentrated in the same region of the same memory chip, which may result in a change in power potential. Contents of the invention [0003] Example devices for high bandwidth memory with multiple channels are disclosed herein. In one aspect of the present disclosure, an apparatus includes: a control chip; a plurality of memory chips stacked on the control ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C5/06G11C5/02G11C5/04H10B12/00
CPCG11C5/025G11C7/1057G11C7/1069G11C5/063G11C7/222H01L25/0657H01L25/18G11C5/06H10B12/00
Inventor 成井诚司
Owner MICRON TECH INC