Verification environment control method and device, platform, equipment and storage medium

Abstract

The invention provides a verification environment control method and device, a platform, equipment and a storage medium. The method comprises the following steps of acquiring running state information of an execution module in a verification environment, according to the running state information, judging whether running of the verification environment has a fault or not, and when the running of the verification environment has a fault, controlling the verification environment to stop running. According to the method and the device, the verification environment simulation hanging can be quickly alarmed, and the simulation is stopped, so that the time loss during simulation hanging operation is greatly reduced, and the iteration of chip verification is accelerated.

Description

technical field [0001] The present application relates to the technical field of chip verification, in particular, to a verification environment control method, device, platform, equipment and storage medium. Background technique [0002] Chip verification is to use the corresponding verification language, verification tools, and verification methods to verify whether the chip design meets the required specifications defined by the chip before chip production, whether the risk has been completely released, and all defects have been found and corrected. [0003] With the rapid development of the integrated circuit industry, the scale and complexity of chips are increasing, and at the same time, the scale and complexity of the verification environment are also greatly increasing. During the running of the verification environment simulation, due to the deadlock or competition inside the chip design, or the possible existence of infinite loops and invalid waits in the verificat...

AI Technical Summary

Problems solved by technology

However, if the simulation operation of the traditional verification environment encounters a hang-up situation, the simulation can only be stopped when the simulation time reaches the TIMEOUT time parameter value, and the period from the encounter of the simulation hang-up to the stop of the simulation is wasted. wasted

And in the actual scene, because all simulation use cases must be considered, the default upper limit of the environment simulation time must be set to a larger value. When an error occurs, it will take a long time to stop the simulation, resulting in the failure to quickly reproduce the error. Affect verification efficiency

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