Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

A high-speed processing method for large data block iteration, FPGA device and system

A large data block, high-speed processing technology, applied in the computer field, can solve problems affecting FPGA processing efficiency, occupying system resources, and limited RAM resources, so as to improve overall efficiency, release system resources, and meet computing needs.

Active Publication Date: 2022-02-22
ZHENGZHOU XINDA JIEAN INFORMATION TECH
View PDF5 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] However, due to the limited RAM resources in the current FPGA, it is difficult to transfer all the large data blocks to the FPGA. Affects the overall processing efficiency of the FPGA

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • A high-speed processing method for large data block iteration, FPGA device and system
  • A high-speed processing method for large data block iteration, FPGA device and system
  • A high-speed processing method for large data block iteration, FPGA device and system

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 2

[0043] The difference between this embodiment and Embodiment 1 is that: in this polling process, the algorithm channel that is determined not to read data this time is executed in the first order to generate the first sorting process; The algorithm channel that reads and whose read length is the threshold value of the single-segment data transmission executes the second sorting process in order to generate the second sorting; reads the data determined this time and the read length is the length of the remaining source data The algorithm channel executes the third sorting process in sequence to generate the third sorting; after this round of polling, the next polling is performed in the order of the first sorting, the second sorting, and the third sorting.

[0044] The above method enables the DMA controller to dynamically adjust the order of the next round of polling according to the computing power of different algorithm channels and the actual transmission situation, so that ...

Embodiment 3

[0046] The difference between this embodiment and embodiment 2 is: as figure 2 As shown, according to the amount of operation data in a single iteration, the source data is read from the front buffer in sections for iterative operation processing, and the operation results are cached in the back buffer; the current available space in the back buffer is not 0 and all When the iterative operation of the source data is completed, the length of the operation result in the back buffer is extracted, and the DMA controller is triggered based on the length of the operation result in the back buffer to write the operation result into the host memory according to the destination address.

[0047] It can be understood that when the source data block is small, the calculation result corresponding to the algorithm channel is also small, so that the calculation result can be written into the host memory at one time.

Embodiment 4

[0049] The difference between this embodiment and embodiment 2 is: as figure 2 As shown, according to the amount of operation data in a single iteration, the source data is read in segments from the front buffer for iterative operation processing, and the operation result is cached in the back buffer; when the current available space of the back buffer is 0, based on The space size of the back buffer triggers the DMA controller to write the operation result into the host memory according to the destination address.

[0050] It can be understood that when the source data block is too large, the calculation result corresponding to the algorithm channel is also too large, so that the calculation result cannot be written into the host memory at one time, and segment writing is required at this time.

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The present invention provides a high-speed processing method, FPGA device and system for large data block iteration. When a certain algorithm channel receives the command word written by the host computer through the PCIE IP core, the source data that has been read is accumulated according to the command word. The length of the current buffer and the size of the current available space in the front buffer determine the length and start address of this read, and generate a DMA request based on the read length and start address to send to the host; the host returns a TLP completion packet according to the DMA request; After the algorithm channel receives the TLP completion packet, it caches the source data in the TLP completion packet to the front buffer, reads the source data from the front buffer sequentially in segments according to the amount of operation data of a single iteration, and performs iterative calculations processing, and after the iteration is completed, write the operation result into the host memory according to the destination address.

Description

technical field [0001] The invention relates to the field of computer technology, in particular to a high-speed processing method for iterative large data blocks, an FPGA device and a system. Background technique [0002] In the information age where information security is increasingly valued by people, data processing and storage products require not only the function of processing data, but also the functions of virus protection and encryption and decryption. In response to this requirement, there are currently two schemes on the market, software encryption and decryption and hardware encryption and decryption, among which hardware encryption and decryption has attracted the attention of researchers because of its fast speed and high security. [0003] Especially for complex algorithms, in order to increase the speed, it is usually completed by hardware, and FPGA is a good solution. FPGA (Field-Programmable Gate Array), that is, Field Programmable Gate Array, is a produc...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06G06F13/28G06F13/40G06F21/60
CPCG06F3/0656G06F3/064G06F3/061G06F13/28G06F13/4022G06F21/602
Inventor 苏庆会冯驰李银龙王斌王中原刘苗苗
Owner ZHENGZHOU XINDA JIEAN INFORMATION TECH
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com