Device and method for fast sampling of bit stream based on fpga

Abstract

The invention relates to the technical field of data sampling, and discloses an FPGA-based bit stream rapid sampling device and method. The device includes a state sampling module, a FIFO buffer module, a single-bit comparison module, a shift sorting module and a judging module. Through the FIFO buffer module, single-bit comparison module, and shift sorting module, the simple shift is replaced by addition and subtraction operations, and the output of the specified bit number of the m-bit shift register is replaced by the bit comparison output, thereby simplifying the entire oversampling process. This enables it to achieve a 40% reduction in resource consumption and logic delay, and provides a solution for higher resource utilization by performing complex synchronous and asynchronous communication on FPGA.

Description

technical field [0001] The invention relates to the technical field of data sampling, in particular to an FPGA-based rapid bit stream sampling device and method. Background technique [0002] In the field of wired communication, in order to save costs and improve reliability, the data interaction between devices is generally carried out by serial communication, and the n-bit data to be transmitted is converted into n-bit stream for serial communication. Send and receive data. Generally, the sending device of the bit stream shifts the n-bit binary data of the sending register to the data line according to a specific bit sequence according to the latch edge of a sending clock provided internally or externally by the sending device, and performs level lock The receiving device of the bit stream samples the level on the data line according to the sampling edge of a receiving clock provided internally or externally by the receiving device, and latches it into the receiving regis...

AI Technical Summary

Problems solved by technology

[0005] The disadvantage of this process is that there are Bit difference, sum calculation and For bit comparison, for FPGA, it is necessary to use multiple lookup tables to complete the search of addition and subtraction results. When the number of oversampling m reaches a certain number, it will also occupy fast carry chain resources. In addition, multiple lookup tables are required to implement bit comparator, higher resource cost

From state sampling to state output, at least 5 modules can complete a sampling filter, which has a certain logic delay and forms a certain bottleneck for high-speed communication

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