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Circuit for synchronizing picture and method therefor

A technology for synchronizing circuits and pictures, applied in the field of video decoders, and can solve problems such as damage

Inactive Publication Date: 2004-01-21
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] When the picture unit decoding time point is determined by the VLD 30 using only the PTS and DTS output from the PES decoder 10, if the PES stream is damaged by an unexpected state such as an error in the transmission path corresponding to the transmitted bit stream, then there will be problems

Method used

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  • Circuit for synchronizing picture and method therefor
  • Circuit for synchronizing picture and method therefor
  • Circuit for synchronizing picture and method therefor

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Embodiment Construction

[0017] Preferred embodiments of a picture decoding synchronization circuit and a picture decoding synchronization method according to the present invention will be described below with reference to the accompanying drawings.

[0018] exist figure 2 Among them, when a packet elementary stream (PES) is input to a PES decoder 100, the PES decoder 100 decomposes the PES stream, selects only PES packets corresponding to a video elementary stream, and deletes the header of the selected PES packet, And output a video elementary data stream. The video elementary data stream is written to and read from a bit buffer 110 according to a hold signal and a skip signal, which will be described below.

[0019] The variable length decoder (VLD) 120 outputs signals defined by the MPEG-2 syntax, which are a picture structure (pic_struct) signal indicating that a transition picture is a frame unit or a field unit, indicating a group of pictures (GOP) where a GOP is detected. ) Header detection...

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Abstract

A picture decoding synchronizing circuit and a picture decoding synchronizing method are provided. When the decoding synchronization is controlled in units of a picture, in a variable length decoder using the transferred PTS and DTS information, the value obtained by adding the previous DTS to an offset is determined to be the DTS value of the current picture, if errors are generated in the transferred PTS and DTS, considering the errors of the transferred bit stream. If no errors are generated in the PTS or DTS, then the transferred PTS and DTS are determined to be the DTS value of the current picture. By controlling the picture decoding using the determined DTS value, the bit buffer does not underflow or overflow and the decoded data is displayed naturally on a screen.

Description

technical field [0001] The present invention relates to a video decoder, and further relates to a synchronous picture circuit and a corresponding synchronous picture circuit for controlling decoding synchronization in units of a picture so that the bit buffer of a variable length decoder (VLD) does not overflow or overflow method. Background technique [0002] In the MPEG-2 (Motion Picture Experts Group) system, a picture can be an I (intra-coded) picture, a B (bidirectionally predictively coded) picture, and a P (predictively coded) picture. MPEG-2 video is coded in units of frames or in units of fields. I pictures can be decoded regardless of other pictures. P pictures can be decoded from previous I or P pictures. A B picture can be decoded from a previous I or P picture and a subsequent I or P picture. When the input includes all I, B and P pictures, it is possible to restore an original picture only by properly controlling the decoding timing and output timing, so th...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N19/102H04N7/24H04N7/62H04N19/00H04N19/166H04N19/172H04N19/177H04N19/196H04N19/423H04N19/46H04N19/463H04N19/65H04N19/67H04N19/70H04N19/91H04N21/43H04N21/44
CPCH04N21/44004H04N21/4307H04N21/43072H04N21/43
Inventor 金圣奉
Owner SAMSUNG ELECTRONICS CO LTD