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Ferroelectric memory array capable of realizing multi-operand memory calculation

A ferroelectric memory and memory array technology, applied in the field of circuits, can solve problems such as high design costs

Pending Publication Date: 2021-11-16
XIANGTAN UNIV
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But multiple operands require more reference current or voltage, which will also bring high design cost

Method used

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  • Ferroelectric memory array capable of realizing multi-operand memory calculation
  • Ferroelectric memory array capable of realizing multi-operand memory calculation
  • Ferroelectric memory array capable of realizing multi-operand memory calculation

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Embodiment Construction

[0027] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0028] Such as figure 1 , figure 2 , image 3 As shown, a ferroelectric memory array that can realize multi-operand memory calculation includes a memory array, a sensing and multi-valued computing unit, a sensing line driver, a forwarding line unit, and an address decoder. The sensing and multi-valued The computing unit is connected to the memory array, and the memory array is connected to the forwarding row unit; the address decoder is connected to the memory array, and is used to select the row or column to be operated and perform bitwise logic operation, and perform a bitwise logic operation in the sensing / multi-valued computing module Obtain the operation result; the sensing and multi-valued calculation unit is connected to the input end of the output buffer, the output end of the output buffer is connected to the first input end of the first dat...

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Abstract

The invention discloses a ferroelectric memory array capable of realizing multi-operand memory calculation, which comprises a sensing and multi-valued calculation unit, a sensing line driver and an address decoder, and is characterized in that the sensing and multi-valued calculation unit is connected with a memory array, and the memory array is connected with a forwarding issuing unit; the address decoder is connected with the memory array; the sensing and multi-valued calculation unit is connected with the input end of the output buffer, the output end of the output buffer is connected with the first input end of the first data selector, the first input end of the second data selector and the input end of the input buffer, and the output end of the first data selector is connected with the forwarding issuing unit; and the output end of the input buffer is connected with the second input end of the second data selector, and the output end of the second data selector is connected with the memory array after passing through the sensing line driver. The architecture is suitable for all resistance-based unit designs, and only N / 2 clock cycles are needed for the CiM operation with N operands.

Description

technical field [0001] The invention relates to the field of circuits, in particular to a ferroelectric memory array capable of realizing multi-operand memory calculation. Background technique [0002] The calculation mechanism of the current storage-computing architecture only considers the calculation of two operands within one clock cycle. This also means that when a command needs to be executed on N rows, it takes N-1 clock cycles to operate. In addition, the existing integrated memory-computing architecture implements bit-wise logic operations mainly by sensing the resulting current / voltage of the bit line and comparing it with the reference current / voltage. But multiple operands require more reference currents or voltages, which will also bring high design costs. Therefore, how to effectively control the number of references when performing multiple operands is an inevitable problem. Contents of the invention [0003] In order to solve the above technical problems...

Claims

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Application Information

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IPC IPC(8): G11C11/22
CPCG11C11/2255G11C11/221Y02D10/00
Inventor 唐明华刘睿陈晓玲李刚燕少安肖永光李正
Owner XIANGTAN UNIV
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