Down-conversion processing system and method for high-speed signal under low-speed clock

Abstract

The invention relates to a down-conversion processing system for a high-speed signal under a low-speed clock, which comprises a sampling module and an FPGA module. The sampling module acquires an analog signal and inputs the analog signal into the FPGA module through analog-digital conversion, and the FPGA module comprises an interface, a plurality of multipliers, an NCO and an accumulator; the interface transmits sampled data to the multiplier, the NCO is connected with the multiplier, the original frequency of the data transmitted by the interface is converted and mapped to the frequency range of the NCO, the data obtained after frequency conversion of the NCO is divided into a real part signal and an imaginary part signal, and the real part signal and the imaginary part signal are accumulated through the corresponding accumulators respectively. The invention further provides a method based on the system. Through a control system of the NCO of the FPGA, down-conversion processing on a high-speed signal under a low-speed clock is realized, multiplier resources of the FPGA are saved to the greatest extent, and the method can be successfully applied to middle and low-end FPGAs with not rich multiplier resources.

Description

technical field [0001] The invention relates to the field of high-speed sampling and analysis of narrow-band signals, in particular to a down-conversion processing system and method for high-speed signals under a low-speed clock. Background technique [0002] At present, the stable working clock of common FPGAs at home and abroad generally does not exceed 300MHz, but high-speed signal sampling can generally reach more than 1G. How to down-convert high-speed signals under low-speed clocks, there are relatively mature methods at present, but these Methods generally require rich FPGA multiplier resources, and accordingly only mid-to-high-end FPGAs can meet the demand. How to realize down-conversion processing of high-speed signals under low-speed clocks on low-end FPGAs with insufficient multiplier resources while ensuring various indicators will be a problem that needs to be solved. Contents of the invention [0003] In order to solve the existing technical problems, the pr...

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Problems solved by technology

[0002] At present, the stable working clock of common FPGAs at home and abroad generally does not exceed 300MHz, but high-speed signal sampling can generally reach more than 1G. How to down-convert high-speed signals under low-speed clocks, there are relatively mature methods at present, but these Methods generally require rich FPGA multiplier resources, and accordingly only mid-to-high-end FPGAs can meet the requirements

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