Accelerator and method for operating same
An operation method and accelerator technology, applied in neural learning methods, complex mathematical operations, biological neural network models, etc., can solve problems such as low efficiency
Pending Publication Date: 2021-11-19
SAMSUNG ELECTRONICS CO LTD
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The tensors involved may be relatively sparse, so computing each element-wise product would result in significant inefficiency since a large fraction of these products would be equal to zero
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[0050] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of exemplary embodiments of the system and method for hierarchical weight preprocessing of neural network accelerators provided according to the present disclosure, and is not intended to represent that the present invention can be constructed or utilized Public only form. This description sets forth the features of the disclosure in conjunction with the illustrated embodiments. However, it is to be understood that the same or equivalent functions and structures can be achieved by different embodiments which are also intended to be encompassed within the scope of the disclosure. As indicated elsewhere herein, like element numbers are intended to refer to like elements or features.
[0051] In computations performed on a neural network (eg, a convolutional neural network), various operations may be performed on tensors of weights and tensors of activations...
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An accelerator and an operation method of the accelerator are provided. The method of operation includes accessing, by a first processing circuit, a weight buffer to perform intra-block pre-processing of a first weight tensor in the weight buffer to form a first pre-processed weight tensor in the weight buffer, and accessing, by the first processing circuit, the weight buffer to perform inter-block pre-processing of a second weight tensor in the weight buffer to form a second pre-processed weight tensor in the weight buffer, wherein the intra-block pre-processing includes storing a first element of a first weight block of the first weight tensor at a second position of the weight buffer, and moving the first element by one position in the forward direction or in the look-aside direction, and the inter-block pre-processing includes moving a first row of a first weight block of the first pre-processed weight tensor by one position in the forward direction or one position in the look-aside direction by storing the first row of the first weight block at a fourth position of the weight buffer.
Description
[0001] This application claims priority and benefit to U.S. Provisional Application No. 63 / 024,676, filed May 14, 2020, entitled "HIERARCHICAL WEIGHT PREPROCESSING FOR NEURAL NETWORK ACCELERATOR" , the entire content of the US provisional application is hereby incorporated by reference. technical field [0002] One or more aspects of embodiments according to the present disclosure relate to accelerators for neural networks, and more particularly, to a system and method for hierarchical weight preprocessing for neural network accelerators. Background technique [0003] Computations performed in neural networks can involve tensor products of weights and activations. The tensors involved may be relatively sparse, so computing each element-wise product will result in significant inefficiency since a large fraction of these products will equal zero. [0004] Therefore, there is a need for a technique for improving the operating efficiency of an accelerator for a neural network. ...
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IPC IPC(8): G06N3/063G06N3/04G06N3/08
CPCG06N3/063G06N3/08G06N3/045G06F17/16G06N3/04G06N7/04G06N3/06G06N3/0464G06N20/00
Inventor 申宗勳阿里·沙菲·阿得斯塔尼哈姆扎·艾哈迈德·阿里·阿卜杜拉齐兹约瑟夫·哈松
Owner SAMSUNG ELECTRONICS CO LTD