Activity analysis method and system for fine-grained variables in multi-beat instruction

Abstract

The invention discloses an activity analysis method and system for fine-grained variables in a multi-beat instruction. The operation modes and effective time of a current instruction and a last operation instruction on variables are compared when each instruction is analyzed under the background of multiple beats of an instruction execution cycle, variable activity is not simply reserved according to 'read after write' and 'read after read', an active interval is newly created in each write operation, an active interval with the interval left end point being smaller than the maximum value of the current beat needs to be found in each read operation, and the interval right end point is updated to be the beat with the current instruction read operation effective. Activity analysis of the fine-grained variables in the multi-beat instruction can be achieved, on the premise that the execution beat and the instruction arrangement sequence of the instruction are determined, activity intervals of all the variables are obtained by traversing all the basic blocks and all the instructions, the period of the variables occupying the register can be obtained through activity analysis, and a judgment basis is provided for distribution and release of registers in the compiler.

Description

technical field [0001] The invention relates to a compiler register allocation technology in a computer program compiler, in particular to a fine-grained variable activity analysis method and system in multi-tick instructions. Background technique [0002] In the field of compilation, in order to make full use of register resources and analyze the conflict relationship of variables, the compiler needs to obtain the active range / lifetime of variables through analysis before allocating registers to variables / operands in instructions. This process Called the activity analysis of variables. [0003] In the traditional architecture, due to resource conflicts, the next instruction can only be executed after one instruction is executed, so the execution of the instruction is always serial, and the execution cycle of the instruction is always designed or regarded as one beat. However, with the increasing diversification of architecture design, in order to make full use of various r...

AI Technical Summary

Problems solved by technology

At the same time, during the compilation process, instruction scheduling and register allocation are often performed alternately multiple times. After assembly instructions are scheduled, the instruction arrangement will be more complicated, resulting in a more complicated judgment process.

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