19 results about "Blocks" patented technology

The invention relates to the technical field of computers, and discloses a method for generating a test program for testing a Solidiity smart contract compiler, which comprises the following steps of: defect directional triggering: inserting a Solidiity variable through an inline assembly block to expose an optimizer defect, and limiting a dynamic array / character string to be expanded to at most one element at a time; semantic consistency control: eliminating intermediate representation behavior differences by adopting a placeholder counter, and preventing border crossing through an array length check instruction; and resource conflict arbitration: managing EVM stack variables by using a block scope, and nesting hierarchies based on a depth threshold truncation function. Through triple innovative design of defect directional triggering, semantic consistency control and resource conflict arbitration, the fundamental contradiction among semantic ambiguity, low defect detection rate and resource constraint in the Solidity compiler test is systematically solved.

Techniques are described herein for translating between low-level languages and high-level languages. A method includes: receiving first source code in assembly language, the first source code including a plurality of code blocks, and each code block of the plurality of code blocks including a plurality of lines of assembly code; for each of the plurality of code blocks: for each of the plurality of lines of assembly code in the code block, processing the line of assembly code to generate a natural language description of the line of assembly code; and processing the code block and the natural language descriptions of the plurality of lines of assembly code in the code block to generate a natural language description of the code block; and processing the natural language descriptions of the plurality of code blocks to generate a natural language description of the first source code.

Apparatuses, systems, and techniques to execute CUDA programs. In at least one embodiment, an application programming interface is performed to indicate one or more attributes of one or more groups of blocks of one or more threads.

This invention discloses a graphical real-world block programming monitoring method and system, relating to the field of children's programming. The method includes: acquiring the outline features of variable blocks, condition blocks, loop blocks, operation blocks, and logical judgment blocks; acquiring at least one basic local structure of the block programming, and pre-acquiring test data and result data of the basic local structure; determining whether the block programming has completed the actual local structure; calculating the overlap ratio between the feature local structure and the basic local structure to be identified; selecting the basic local structure to be identified with the largest overlap ratio as a similar local structure of the feature local structure; acquiring test data and result data of similar local structures; obtaining the target local structure; obtaining feature result data; and comparing the feature result data with similar result data for consistency. By setting up a structure recognition module, a data acquisition module, an instruction adjustment module, and a comparison module, children can complete self-correction, ensuring their interest in learning.

The invention discloses a cross-ISA (Industrial Standard Architecture) extension program translation method based on binary rewriting, which comprises the following steps of: 1) naming an instruction set ISA of a program to be translated as an original ISA, and naming an instruction set ISA on target hardware for running original ISA extension as a target ISA; 2) performing comparative analysis on a binary file corresponding to the original ISA extension compilation and a binary file corresponding to the target ISA extension compilation to obtain an instruction needing to be translated relative to the target ISA extension in the original ISA extension, and segmenting the instruction into a plurality of program basic blocks needing to be translated; 3) allocating a jump instruction and an address space for translating and storing translated codes to each program basic block; (4) distributing the program basic blocks into the corresponding address spaces through a jump instruction to carry out static binary translation, and generating a static file; and (5) distributing a loading address for the static file by utilizing a loader according to the address distribution information in the static file, and loading the static file to a corresponding position.

The present invention relates to the field of compiler technology, and discloses a code compilation method, apparatus, device, and medium. The method comprises: obtaining assembly code to be compiled; obtaining target code variable blocks that meet preset standards in the assembly code based on a preset search algorithm; encapsulating the target code variable blocks and determining corresponding macro functions; and executing code compilation based on the macro functions. The present invention optimizes the assembly code to be compiled by merging identical target code variable blocks, using a preset search algorithm to determine consistent target code variable blocks, and encapsulating and determining macro functions to be compiled based on the target code variable blocks. This greatly improves the speed of program search, reduces the total number of code instruction bytes, reduces program memory, speeds up execution, and further improves the compilation efficiency of assembly language.

In various implementations, systems and methods for reducing neural network processing are provided. A compiler can generate instructions from source code of a neural network having a set of repeatable operations. The instructions can include a plurality of blocks. The compiler can add override instructions to the plurality of blocks that trigger an override action when executed by one or more execution engines. The override action causes instructions of a subsequent block to be overridden with NOP instructions. The override action is triggered only when a condition is met.

The invention discloses a front end side JS code intelligent compiling method and device and a medium, and relates to the technical field of computer program compilation, the method comprises the following steps: parsing a target function corresponding to a service request, and obtaining a plurality of to-be-compiled code blocks according to a pre-constructed code splitting index; the method comprises the following steps: acquiring runtime environment data of a client in real time, and generating compiling priority information; generating a compiling instruction sequence according to the compiling priority information through a preset compiling scheduler; performing real-time compiling through an end side compiling engine to generate a corresponding executable code; when it is detected that the source code of any to-be-compiled code block is changed, determining a change influence range; and performing incremental compiling on the recompiled atomic code blocks in the change influence range to generate corresponding new executable codes. Through end-side on-demand compilation and change of an influence range tracking mechanism, dynamic on-demand compilation and accurate incremental updating of front-end JS codes are realized, and the application loading efficiency and the resource utilization rate are remarkably improved.

The invention discloses a compiling and explaining method, system and device for a high-level language of a functional block and a medium, and belongs to the technical field of industrial control systems.The compiling and explaining method comprises the steps that compiling rules are defined; reading a high-level language program file, and generating a binary operation code file according to the compiling rule; downloading the binary operation code file to a configuration interpreter for execution; wherein the step of generating the binary operation code file comprises the substeps of mapping a keyword of a high-level language into an operation code, and compiling a variable into an operand; according to the compiling and explaining method, system and device for the high-level language of the functional block and the medium, a set of compiling and explaining method is self-defined for compiling and explaining the high-level program language of a functional block combination, and program codes can be compiled into binary operation codes; the key codes and the operation codes are presented in the form of a hash table, so that the compiling and explaining speed is increased; the method has good trafficability, correctness and high efficiency.

An exemplary system and method are disclosed for facilitating users in building programs through an assembly of physical objects. In some implementations, the exemplary system and method include (i) a plurality of physical coding blocks and (ii) an interface configured to recognize a combined sequence of physical blocks in the assembly, extract programming functions or logics from the recognized combined sequence, and generate compilable or interpretable code for a software development environment that can be compiled thereon into computer-readable instructions to program electronic devices.

Aspects of the subject disclosure may include, for example, obtaining code data from a plurality of repositories that each include a particular domain-related code (e.g., network domain-related code); generating a NLP model based on the code data; receiving input (e.g., via an API or other technique) where the input includes a natural language statement from equipment of a programmer, and where the natural language statement indicating an intent of the programmer to generate a particular domain-specific code compatible with the particular domain-related code; generating, according to the intent of the programmer, a code block by applying the NLP model to the natural language statement; and providing the code block for presentation at the equipment of the programmer. Other embodiments are disclosed.

This invention discloses a compiler optimization method, system, medium, and device based on basic blocks. The method includes: obtaining a machine code function to be optimized, the machine code function including several basic blocks; sequentially performing optimization operations on each basic block to obtain an optimized machine code function; wherein, for each basic block, the optimization operation includes: identifying instructions to be optimized within the basic block that belong to custom affine operations, the custom affine operations supporting at least two custom operation types; matching the operation type and modifier of the instructions to be optimized according to a preset affine factor mapping table; performing affine constant folding optimization on the successfully matched instructions to be optimized, and updating the affine factor mapping table according to the optimization result; and outputting the optimized machine code function so that the hardware device executes the optimized machine code function. This invention can significantly reduce the number of instructions, thereby improving running efficiency, while ensuring the correctness of optimization.

The present invention relates to a method for operating an information technology system, in which a program code usable by a processor for processing at least one task (1.1, 1.2) is divided by a compiler into at least two functional blocks (2) during a compilation step, which are arranged in a data flow graph (3), and the compiler analyzes the data flow graph (3) to determine the execution order of each functional block (2) by the processor. The method according to the present invention is characterized in that, when processing the at least one task (1.1, 1.2), the compiler identifies functional blocks (2) that can be executed in parallel by the processor, checks for each group (4) of functional blocks (2) that can be executed in parallel whether at least program code portions of at least two functional blocks (2) require the execution of the same instruction (5) by the processor, and assigns these program code portions to the same execution unit of the processor for simultaneous processing according to a single instruction, multiple data approach.

The present application relates to the technical field of computer, and discloses a bytecode optimization method and device for executable files and electronic equipment.The method comprises the following steps: dividing the bytecode of the functions of the executable file into blocks to obtain a plurality of program blocks; when a register assignment constant instruction is searched in the program block, judging whether the register in the subsequent instruction of the register assignment constant instruction is replaced by a preset assignment constant; if yes, judging whether there is an instruction taking the first register as a source register or a target register after the register assignment constant instruction in the program block to obtain a preliminary deletion optimization judgment result; judging whether there is an instruction branching out of the program block after the register assignment constant instruction in the program block; if yes, judging whether there is an instruction taking the first register as a source register in the program block jumped to; if yes, marking the register assignment constant instruction as an instruction that cannot be deleted and optimized, otherwise marking the register assignment constant instruction as a target instruction that can be deleted and optimized; and traversing each program block until the judgment on each register assignment constant instruction is completed and the register assignment constant instruction marked as the target instruction that can be deleted and optimized is deleted.The present application directly optimizes the compiled bytecode by performing the deletion and optimization of the register assignment constant instruction on the bytecode of each function, thereby reducing the size of the executable file and improving the execution speed.

The present application relates to the technical field of visual programming, and discloses a generation method and system of visual programming blocks, an electronic device and a storage medium, the method comprising: acquiring block function requirement information in the form of program code; performing artificial intelligence understanding and analysis on the block function requirement information to obtain block structured metadata; determining the block type and attribute information of a target block according to the block structured metadata, and determining the configuration parameters of the target block according to the block type and attribute information; and generating a standardized configuration file of the target block based on the block type, attribute information and configuration parameters. The present application converts the graphical configuration understanding problem, which is not good at artificial intelligence, into the code program semantic understanding, which is good at artificial intelligence, can automatically generate block configuration files conforming to the specification, reduces the block development technical threshold and maintenance cost, reduces the artificial errors caused by manual intervention, shortens the development cycle, improves the development efficiency and standardization, and meets the demand for rapid iteration and expansion of the platform.

A system includes a compiler including a plurality of compiler blocks. The compiler blocks of the plurality of compiler blocks are compossible. The compiler is configured to identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code. The compiler is further configured to determine one or more processing operations to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The compiler is configured to compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.

A system includes a compiler including a plurality of compiler blocks. The compiler blocks of the plurality of compiler blocks are compossible. The compiler is configured to identify one or more resources in a hardware to execute a set of low-level instructions that is generated from a high-level function in a high-level code. The compiler is further configured to determine one or more processing operations to be performed that is associated with the high-level function in the high-level code. The determining of the one or more processing operations occurs based on architecture of the hardware. The compiler is configured to compile the high-level function in the high-level code of the application into the set of low-level instructions to be executed on the hardware.

Operating program writing system (10) that writes an operating program of a system (1) consisting of a peripheral device and a robot (2), wherein the operating program writing system comprises: a block memory section (11) configured to store a plurality of blocks, each of which is a unit of work constituting the operating program, a selection section (12) which is configured to select by it any number of blocks to be combined to form the operating program from the multitude of blocks stored in the block memory section, a display section (13) configured to display a path diagram in which any number of blocks selected by the selection section are arranged according to a user-defined order such that they form the operating program, a selection and input section (14) which is configured to accept the selection of at least one block from among any number of blocks displayed on the display section and through which arguments of the selected at least one block can be entered, a sequence section (15) which is set up to arrange sequence buttons (A) for any number of blocks on the display section and to allow, through the selection and input section, only those blocks that correspond to the sequence buttons and whose sequence buttons have been pressed, a write section (16) configured to use i) any number of blocks selected by the selection section, and ii) the input argument of the at least one block selected by the selection and input section as the basis for writing the operating program, and a setting section (17) which is set up to parse an existing operating program and to set a variety of blocks and arguments contained in the blocks from the existing operating program, wherein: - the blocks include a variety of position blocks (P1, P2, P3, P4) that teach which positions the robot moves to, and a variety of logic blocks (L1, L2, L3, L4, L5, L6) that teach which types of operations are to be performed, - the multitude of blocks selected by the selection section includes at least one positional block and at least one logical block, - the operating program consists of a multitude of lines, with the set section set up to evaluate the attribute of each line as either a logic attribute, a control signal attribute, or a position attribute, and - the set section is further set up to i) write a line of a position attribute and a line of a logic attribute as independent blocks and ii) assign lines of a control signal attribute that follow a line of a logic attribute to the same block as the related line of the logic attribute, in order to set the logic blocks and the position blocks and to set the arguments contained in the blocks.

The invention discloses a visual programming method and device, equipment, a storage medium and a program product, and belongs to the technical field of computers. The method comprises the steps that a programming interface is displayed, the programming interface comprises at least one programming building block, and the programming building blocks are used for representing basic elements for generating program codes; in response to a change operation of an association relationship of a first programming building block in the programming building blocks, determining availability of the first programming building block; the first programming building blocks in a first state or a second state are displayed based on the availability of the first programming building blocks, the first state represents that the first programming building blocks are used for generating program codes corresponding to the first programming building blocks, and the second state represents that the first programming building blocks are limited to generate the corresponding program codes. According to the method, whether the first programming building block is available or not can be visually known by displaying the first state or the second state of the first programming building block, the correct first programming building block can be selected in the programming process, the programming difficulty is reduced, and the programming efficiency is improved.