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Formation method of semiconductor structure

A semiconductor, fin-shaped technology applied in the field of fin width trimming steps

Pending Publication Date: 2021-12-21
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The first deposition rate is greater than the second deposition rate

Method used

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  • Formation method of semiconductor structure
  • Formation method of semiconductor structure
  • Formation method of semiconductor structure

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Embodiment Construction

[0040] The following content can be combined with figures to facilitate understanding of the embodiments of the present disclosure. In the drawings, like numbers generally indicate identical, functionally similar, and / or structurally similar elements.

[0041] It should be noted that "one embodiment", "an embodiment" and "example embodiment" in the specification indicate that the embodiment may include specific structures or characteristics, but each embodiment does not necessarily include specific structures or characteristics. Moreover, these terms are not necessarily referring to the same embodiment. In addition, when the embodiment describes specific structures or characteristics, those skilled in the art can combine other embodiments to realize these structures or characteristics, whether or not explicitly stated.

[0042] It should be understood that the purpose of the wordings or phrases herein is for illustration rather than limitation, and therefore those skilled in ...

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Abstract

A semiconductor structure and a method of forming the same are described. The semiconductor structure may include a substrate, a first fin structure having a first height and a first width and formed on the substrate, a second fin structure having a second height and a second width and formed on the substrate, and an insulating stack formed on underside portions of the first fin structure and the second fin structure. The second height may be substantially equal to the first height, and the second width may be greater than the first width. An upper surface of the insulating stack may be lower than upper surfaces of the first fin structure and the second fin structure.

Description

technical field [0001] Embodiments of the present disclosure relate to semiconductor structures, and in particular to providing different fin width trimming steps (eg, etch) in different regions of an integrated circuit. Background technique [0002] FinFETs may have a fin structure to improve gate control over the channel region. The dimensions of the fin structures may vary in different regions of the integrated circuit. These fin dimensional variations degrade integrated circuit performance. Contents of the invention [0003] In some embodiments, the method for forming a semiconductor structure includes: forming a first fin structure and a second fin structure on a substrate; depositing an insulating layer on the first fin structure at a first deposition rate and a second deposition rate respectively. on the upper surface and the upper surface of the second fin structure; and removing a part of the insulating layer to expose the upper surface of the first fin structur...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8234H01L29/10
CPCH01L21/823412H01L21/823431H01L29/1033H01L29/66818H01L29/785
Inventor 刘书豪詹前泰陈亮吟张惠政杨育佳陈思颖
Owner TAIWAN SEMICON MFG CO LTD