Multi-channel DMA interactive design method based on PCIe bus

Abstract

The invention belongs to the field of data transmission, and provides a multichannel DMA interactive design method based on a PCIe bus. Data transmission is carried out through the PCIe bus on the basis of an FPGA + CPU framework, the mode that the FPGA initiates and ends the DMA reading process actively is adopted, the flexible and controllable function of the DMA packet length is achieved, and the bus utilization rate during DMA transmission is increased; by adopting a mode of reporting DMA packet information instead of interruption, the reporting of DMA transmission completion information is realized, and the adverse effects of jamming or crash and the like which may be brought to an operating system by too frequent interruption are avoided; and by adopting a mode of distributing multiple groups of DMA memories and reporting memories for alternate use during DMA transmission, the functions of simultaneous transmission and data caching of multi-channel DMA are realized. The design of the invention is more suitable for the application occasion that the DMA length continuously changes and the CPU cannot know the DMA length in advance.

Description

technical field [0001] The invention belongs to the technical field of data transmission. Background technique [0002] Direct memory access (Direct Memory Access, DMA) is a common method of data transmission between FPGA and CPU. It means that data transmission does not require CPU intervention, and a large amount of data is exchanged directly between IO devices (such as FPGA) and memory. the transmission method. [0003] figure 1 It is a common single-channel DMA interaction method when the FPGA and the CPU communicate through the PCIe bus. Generally, the CPU first allocates the DMA memory space, and then writes the first address of the DMA memory space and the DMA length to the FPGA through the registers R1 and R2 of the BAR space. , and then write the "DMA start" command (register R3) to the FPGA, and the FPGA starts a DMA data transmission after receiving the DMA start command. After the transmission is completed, the FPGA initiates a DMA completion interrupt to the C...

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a multi-channel DMA interactive design method based on the PCIe bus, to solve the problem of DMA transfer efficiency caused by CPU initiation and frequent interruptions for each DMA transfer, and to solve the problem that the length of each DMA transfer is a fixed value or inflexibility that needs to be set in advance by the CPU

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