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DSP and processing method thereof for loop jump instruction

A jump instruction and processor technology, applied to the architecture with a single central processing unit, machine execution device, general-purpose stored program computer, etc., can solve the problem of low processor efficiency, achieve faster processing speed, and improve processing efficiency , the effect of reducing demand

Pending Publication Date: 2022-01-18
SHENZHEN CHUANGCHENG MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is to provide a DSP processor and a processing method of a loop jump instruction thereof, so as to solve the problem in the prior art that three pipeline cycles are required to execute a loop jump instruction, resulting in low processor efficiency

Method used

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  • DSP and processing method thereof for loop jump instruction
  • DSP and processing method thereof for loop jump instruction

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Embodiment 1

[0059] Based on Embodiment 1 of the present invention, Embodiment 3 of the present invention provides a DSP processor, such as Image 6 As shown, the DSP processor 10 includes an instruction fetch unit 1, a decoding unit 2, and an execution unit 3, wherein the instruction fetch unit 1 is used to read the loop jump instruction assembly program in the instruction fetch stage of the pipeline cycle, wherein The loop jump instruction assembler includes a register address for storing the loop jump instruction variable, a loop jump threshold, a variable processing label, and a jump target address, and the pipeline cycle includes at least an instruction fetch stage, a decoding stage, Execution stage; the decoding unit 2 is used to decode the read loop jump instruction to obtain the decoded loop jump instruction information; the execution unit 3 is used to execute the jump according to the decoded loop jump instruction information Operate or perform a corresponding operation on the cur...

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Abstract

The invention discloses a DSP and a processing method thereof for a loop jump instruction. The method comprises the following steps: reading a loop jump instruction assembly program in an instruction fetching stage of a pipeline period, wherein the loop jump instruction assembly program comprises a register address for storing a loop jump instruction variable, a loop jump threshold value, a variable processing label and a jump target address, and the assembly line period at least comprises an instruction fetching stage, a decoding stage and an execution stage; decoding the read loop jump instruction to obtain the decoded loop jump instruction information; and according to the value of the variable in the register and a cyclic jump threshold, judging whether jump is needed or not, if so, jumping to the jumping target address, and otherwise, carrying out cyclic processing on the value of the variable according to a cyclic processing mode in the cyclic jump instruction. The method improves the processing efficiency of the DSP processor.

Description

technical field [0001] The invention relates to the technical field of instruction processing, in particular to a DSP processor and a method for processing loop jump instructions thereof. Background technique [0002] In the prior art, it generally needs 3 pipeline cycles to execute the loop jump instruction. Taking the for loop of C language as an example, if the (i=0; i<=0x1F; i++) loop is to be realized, the assembler generally needs to write three lines instructions, such as: [0003] [0004] Among the above three instructions, the first instruction I1 is used to judge whether the value of the variable in the register R31 is equal to 0x1F, and store the comparison result in the status register, the second instruction I2 executes the increment of the R31 register, and the third The first instruction I3 decides whether to perform a branch jump according to the flag status register. It can be seen that, in the prior art, it takes 3 pipeline cycles to execute a for ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F15/78G06F9/30
CPCG06F15/78G06F9/30094
Inventor 梁小江谢柱能蒲莉娟黄祯福
Owner SHENZHEN CHUANGCHENG MICROELECTRONICS