Packaging structure and packaging method of high-power radio frequency device

Abstract

The invention discloses a packaging structure of a high-power radio frequency device, which comprises a plurality of radio frequency power chips connected in parallel and a packaging flange. The plurality of radio frequency power chips are obliquely arranged in a packaging inner cavity of the packaging flange, so that the number of input leads of the radio frequency power chips is reduced, and the input leads and output leads are not overlapped in space. The plurality of chips are obliquely arranged on the packaging flange, so that the utilization rate of the packaging space is remarkably improved, and the purpose of higher power output is achieved. By slightly reducing the number of the input leads of the intermediate radio-frequency power chip, the output leads cannot be reduced, the reliability of a high-power application process can be ensured, large-area overlapping of the input leads and the output leads in space is avoided, mutual inductance is reduced, and oscillation of the radio-frequency power device is effectively avoided.

Description

technical field [0001] The invention relates to the technical field of packaging of radio frequency devices, in particular to a packaging structure and a packaging method of high-power radio frequency devices. Background technique [0002] Mainstream RF power chips usually consider factors such as product performance and heat dissipation, and the size of the chip is mostly rectangular with a large aspect ratio. Limited by the production and assembly process, a single chip will not be made very large. When the output power of a single chip cannot meet the requirements, most of them are assembled in the same package by using multiple chips in parallel. At present, the internal chip layout structure of mainstream high-power RF power amplifier devices is as follows: figure 1 shown, combined with figure 2 As shown, multiple chips 1 are assembled in parallel inside the same package 4, the chip 1 is parallel to the package cavity 5, multiple chips 1 are welded side by side on th...

AI Technical Summary

Problems solved by technology

At present, the internal chip layout structure of mainstream high-power RF power amplifier devices is as follows: figure 1 shown, combined with figure 2 As shown, multiple chips 1 are assembled in parallel inside the same package 4, the chip 1 is parallel to the package cavity 5, multiple chips 1 are welded side by side on the package flange 6, and the lead wire (Bond-wire) direction of the chip 1 is in line with the chip welding The direction of the plate (BondPad) is vertical, and the other ends of the input lead 3 and the output lead 2 are soldered to pin 7. The input lead 3 and the output lead 2 will not cross over the chip 1, and there will be no space between the input lead 3 and the output lead 2. However, limited by the size of the chip and the size of the internal cavity of the package, it is impossible to achieve the purpose of higher power output

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